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Need help for an integrator design!

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asic_ant

asic_ant

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The schemetic is attached below.
The aim is as follows:for a given period clock signal with any duty cycle,the Integrator will translate it into DC(with little ripple) voltage proportional to the period.(I'm not sure is it the so called frequency-to-voltage converter).
Besides,the clock amplitude is vdd to gnd,the same as OP's supply.

Then my question is:
1.is R2 necessary;
2.what's the requirement for the OP?BW,SR,Gain...

Any good ideas or related document?
Thanks in advance.
 

R2 is necessary. If R2 is omitted, The offset voltage of the OP will be integrated, leading the output of OP saturated.
 

    asic_ant

    asic_ant

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For single supply and moderate frequencies ~tens of Meg, I believe LM358 will do the job

well, I couldnt figure you mean discrete or integrated implementation..

of coures For integrated the life is a bit different, of course the integrator must be stable, the GBW must be much larger than clock frequency and the R2*C time const must give a pole that is much lower than the clock frequency, in order to work as integrator not low pass filter...the slew rate must be large enough not to limit output swing
 

    asic_ant

    asic_ant

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Still wandering what if the OP's GBW is small than the clock frequency,now that we don't mean to amplify it?
 

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