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Floorplanning is the process of defining the chip-size, placing the macrocell and placing I/O pads.
At this stage you can do an estimate for routing requirements etc.
Floorplanning is the process of creating core and IO areas with rows defined in the core area. Each row will be divided into a minimum unit of area called SITE. Any placed cell will occupy one or more of these sites. The floorplan can be created as soon as the netlist and the LEF is read into the backend tool. After the foorplan the you can get parameters like area of the die, utilization etc.
Sometimes rough placement of blocks is also included in the floorplan. For example, ameoba placement in SOC-E is also part of floorplan. Hope this helps
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