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rom interface in verilog

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siva_7517

siva_7517

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hi,

I am using ROM for my design. Well, I will generate this using a ROM generator from ARTISAN. Below is an example of a rom coding:


module rom (clk, addr, data);
input clk;
input [1:0] addr;
output [1:0] data;
always @ (posedge clk)
case (addr)
2'b00 : data <=2'b01;
2'b01 : data <=2'b10;
2'b10 : data <=2'b11;
2'b11 : data <=2'b00;
endcase
endmodule

above is the example of the data that i would like to keep in the rom.
Lets say, i am doing some multiplication in my design:

assign A =B*C

If i need the B value from addr 2'b00 from the ROM, how can i do the code in verilog to call the value from the ROM?
Hope anyone can help me on this.

Siva
 

I don't know whether I fully understand what you talked, just try to answer it:
if you want to realize the function
(1) give the ROM module the address 2'b00;
(2) the data from the address 2'b00 will be availble at the next cycle of ROM's output.
(3) multiply the data by C,then you get A.

as for the code:

module top(......)

ROM inst_ROM(.clk(clk),.addr(addr),.data(data));
A=data*C;
endmodule
and the 2'b00 is given to addr port of the ROM in the testbench.
 

    siva_7517

    siva_7517

    Points: 2
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how can i do address generation for rom, because i dont want to use the testbench.
 

I am not sure whether I understood your question correctly.
Here is my view.
If you don't want to use the TB to generate rom address, we can use 2bit counter in the top module. For every clock(or based on your control) the counter will be incremented by 1. So that you will get the following seq.
00
01
10
11
port map this counter to your rom address.
Please let me know if my understading about ur question is wrong.
Regards,
Sakthi.
 

    siva_7517

    siva_7517

    Points: 2
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