To declare a user defined primitive in Verilog

verilog primitive

Hi All,

Below is the example code I am trying to Synthesize in Xilinx ISE 8.1:

///////////////Example code to declare a UDP and use it in a module////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

If you synthesize this code in Xilinx ISE 8.1 you will be able to reproduce the following error:

ERROR:Xst:850 - "top.v" line 28: Unsupported Switch or UPD primitive.

Please let me know if its ok to declare a UDP outside a module in any Verilog_Module.v source or there is there something wrong with this declaration...
I tried declaring the UDP with in the module and that did not work either...
Appreciate for your time and help.

Regards
Jayanth

primitive verilog

Hi
I want to ask
do you have passed compilation on any other tool.

thanks

verilog primitives

No, as of now the only tool I have access to is Xilinx ISE 8.1. What other tools are you looking at??? I think it should work even on Xilinx ISE cuz I have pulled up the example code from Xilinx web resources...
This information can be found here: **broken link removed**.

Thanks
Jayanth

user defined primitive

According to the XST guide, UDP is not supported for synthesis.

That means it can be used in simulation only.

See **broken link removed**