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Why use FPGA not CPLD to interface high speed ADC

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Kaka_fsk

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Hi, guys,

Having seen some examples which use FPGA to interface high speed ADC, I just would like to know why not use CPLD to the same job. What is the advantage of FPGA over CPLD in this job. Thanks.

Karl
 

fpga has more logic and ram memories.
cpld if faster, but adc is not that fast even if it is high speed.
 

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    Kaka_fsk

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because the FPGA have pin with double rate speed. SO. It's can read the ADC with half speed!
 

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    Kaka_fsk

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