yasser_shoukry
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I have a problem with using "defparam" with my modules.
I was developing a digital watch module. I developed a counter module to use it inside the digital module.
The counter has a parameter called "max_counts" which is used to define max number of counts after which the counter should overflow:
module counter (clk, reset, counts, clk_out);
.......
.......
parameter max_counts = 4'd9;
.......
endmodule;
Then in the dig_watch module, I instantiated six counters from this module :
module dig_watch(clk, reset, sec0, sec1, min0, min1, hr0, hr1);
.......
.......
defparam C0.max_counts=4'd2;
Counter C0 (...,...,...,....);
......
......
endmodule;
The problem is, when i compile this design on FPGA Advantage , an error message apears at the line of the defparam tells that "using defparam is unsynthesisable"!!!
Can any body help me??
Thanks and Best Regards.
Yasser.
I was developing a digital watch module. I developed a counter module to use it inside the digital module.
The counter has a parameter called "max_counts" which is used to define max number of counts after which the counter should overflow:
module counter (clk, reset, counts, clk_out);
.......
.......
parameter max_counts = 4'd9;
.......
endmodule;
Then in the dig_watch module, I instantiated six counters from this module :
module dig_watch(clk, reset, sec0, sec1, min0, min1, hr0, hr1);
.......
.......
defparam C0.max_counts=4'd2;
Counter C0 (...,...,...,....);
......
......
endmodule;
The problem is, when i compile this design on FPGA Advantage , an error message apears at the line of the defparam tells that "using defparam is unsynthesisable"!!!
Can any body help me??
Thanks and Best Regards.
Yasser.