Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

SDF annotation reduces delay?

Status
Not open for further replies.
E

eruisi

Member level 4
Member level 4
Joined
Jan 3, 2006
Messages
71
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Location
CA
Activity points
1,817
sdf annotation

An interesting finding:
Signal delay in the simulation of synthesized netlist (in verilog) without SDF annotation is larger than the delay in the simulation of the same netlist with SDF annotation.

Same thing happens to post-layout netlist.

I have thought SDF provides delay information for interconnects, so the signal delay should increase with SDF annotation.

Anyone can explain this?
Thanks!
 

annotation delay

i have to check the standard cell verilog model on the "specify" parts.

can you give me the exact timing difference between the two paths, and the detail logic of the path.

thanks

Added after 37 minutes:

i checked verilog model.
with no SDF, "specify" model are used, which is totally inaccurate.

while the SDF is extracted from the cell lib and .spef file, the cell delay is quite accurate.

so, it doesn't make any sense to compare the above two type of delay.
 

    E

    eruisi

    Points: 2
    Helpful Answer Positive Rating
delay specify default without sdf

I generated verilog netlist and sdf file (write_sdf) in design_compiler, and simulated this netlist with sdf file.

Then, I generated verilog netlist and sdf file (SDF out...) in Astro after P&R, and simulated in the same way.

I found the delay in the first case is less than the delay in the second one. After checking two sdf files, I found that sdf file from design_compiler doesn't contain any delay information on interconnection but sdf file from Astro does. Gate delays in both files are similar.

The question is: why SDF file with interconnection delay generates less signal delay?

Thanks a lot!
 

sdf annotation verilog

DC estimate the delay from wireload model,
while Astro estimate the delay from TLU/TLUplus model.

since logic synthesis doesn't has geometry information, the estimated wireload could be much pessimetic.

and it is also no use to compare the two sdf.

actually, only the sdf generated from starRC is used post simulation. you should check the general design flow for right post-simulation flow.
 

    E

    eruisi

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top