Problems of post-simulation in ncverilog

ncverilog no timing check

I finished place&route. Then I dumped out .sdf and .v and simulate the verilog file with SDF timing annotation.

I got the following hunderds of error messages:

ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check (RECOVERY (posedge RN) (negedge CKN) (0.2019)) of instance sdm.modulator_accd3_dd_reg_7_ of module SDFFNRX2 <../layout/design.SDF, line 8911>.
......

line 8911 of design.SDF:
(RECOVERY (posedge RN) (negedge CKN) (0.0000:0.2019:0.2019))

corresponding info in design.v
SDFFNRX2 modulator_accd3_dd_reg_7_ (.CKN(n217), .D(n185), .Q(
modulator_d4_7_), .QN(n415), .RN(n19), .SE(n385), .SI(n416));

I have no idea how to fix them since I don't know the reason for these messages.
Because of design hierachy or because of the way I dumped out .v or .sdf files?

Thanks a lot!

sdf annotation issues in bus signals

Hi,
Show us the module definition of SDFFNRX2. WHat this error means is the following:

A Recovery check is specified bet'n a control signal - "RN" and a clock signal "CKN" while a path didn't exist in your source code. Look inside that module SDFFNRX2 for the same.

HTH
Ajeetha, CVC
www.noveldv.com

setuphold notifier

This is the verilog file from the tsmc library

`timescale 1ns/1ps
`celldefine
module SDFFNRX2 (Q, QN, D, SI, SE, CKN, RN);
output Q, QN;
input D, SI, SE, CKN, RN;
reg NOTIFIER;
supply1 xSN;
supply1 dSN;

buf XX0 (xRN, RN);
not IC (clk, CKN);
udp_dff I0 (n0, n1, clk, xRN, xSN, NOTIFIER);
udp_mux I1 (n1, D, SI, SE);
buf I2 (Q, n0);
not I3 (QN, n0);
and I4 (SandR, xSN, xRN);
and I5 (SandRandSE, SandR, SE);
not I6 (SEb, SE);
and I7 (SandRandSEb, SandR, SEb);
xor I8 (DxorSD, D, SI);
and I9 (flag, DxorSD, SandR);
specify
specparam
tplh$RN$Q = 1.0,
tphl$RN$Q = 1.0,
tplh$RN$QN = 1.0,
tphl$RN$QN = 1.0,
tminpwl$RN = 1.0,
tminpwh$RN = 1.0,
tsetup$RN$CKN = 1.0,
thold$RN$CKN = 0.5,
tplh$CKN$Q = 1.0,
tphl$CKN$Q = 1.0,
tplh$CKN$QN = 1.0,
tphl$CKN$QN = 1.0,
tsetup$D$CKN = 1.0,
thold$D$CKN = 0.5,
tsetup$SI$CKN = 1.0,
thold$SI$CKN = 0.5,
tsetup$SE$CKN = 1.0,
thold$SE$CKN = 0.5,
tminpwl$CKN = 1.0,
tminpwh$CKN = 1.0;
// path delays
if (SandRandSEb)
(negedge CKN *> (Q +: D)) = (tplh$CKN$Q, tphl$CKN$Q);
if (SandRandSE)
(negedge CKN *> (Q +: SI)) = (tplh$CKN$Q, tphl$CKN$Q);
( negedge RN *> (Q +:1'b0) ) = (tplh$RN$Q, tphl$RN$Q );
if (SandRandSEb)
(negedge CKN *> (QN -: D)) = (tplh$CKN$QN, tphl$CKN$QN);
if (SandRandSE)
(negedge CKN *> (QN -: SI)) = (tplh$CKN$QN, tphl$CKN$QN);
( negedge RN *> (QN -:1'b0) ) = (tplh$RN$QN, tphl$RN$QN );

// timing checks
$setuphold(negedge CKN &&& (SandRandSEb == 1), posedge D, tsetup$D$CKN ,thold$D$CKN , NOTIFIER);
$setuphold(negedge CKN &&& (SandRandSEb == 1), negedge D, tsetup$D$CKN ,thold$D$CKN , NOTIFIER);
$setuphold(negedge CKN &&& (SandRandSE == 1), posedge SI, tsetup$SI$CKN ,thold$SI$CKN , NOTIFIER);
$setuphold(negedge CKN &&& (SandRandSE == 1), negedge SI, tsetup$SI$CKN ,thold$SI$CKN , NOTIFIER);
$setuphold(negedge CKN &&& (flag == 1), posedge SE, tsetup$SE$CKN ,thold$SE$CKN , NOTIFIER);
$setuphold(negedge CKN &&& (flag == 1), negedge SE, tsetup$SE$CKN ,thold$SE$CKN , NOTIFIER);
$width(negedge CKN &&& (SandR == 1), tminpwl$CKN, 0, NOTIFIER);
$width(posedge CKN &&& (SandR == 1), tminpwh$CKN, 0, NOTIFIER);
$setuphold(negedge CKN, posedge RN, tsetup$RN$CKN ,thold$RN$CKN , NOTIFIER);
$width(negedge RN, tminpwl$RN, 0, NOTIFIER);
endspecify
endmodule // SDFFNRX2
`endcelldefine

Any further suggestions?

Thanks

&&&(sandr==1)

Hi,
If I read your model (Verilog) correctly I fail to see any $recovery check at all and hence is the ncelab's error.

SDF LRM states:

SDF LRM said:

It is assumed that the timing models
used by the design are described to the analysis tool by some means other than the SDF file. Thus, when
using SDF, it is crucial that the data in the SDF file be consistent with the timing models.

Click to expand...

In your case, there is a RECOVERY spec in SDF with no corresponding check in the "timing model" - i.e. in your netlist.

Looks like you need an updated Cell library model. It may also be that your design is fully synchronous and hence you can safely ignore these asynchronous checks.

HTH
Ajeetha, CVC
www.noveldv.com
New Book: A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
https://www.systemverilog.us/

$setuphold notifier

Thanks for your kindly help!

Here is my trouble:

I successfully P&Red a simple design and dumped .v and .SDF out.
When I post-simulated .v, if I back-annoted with .SDF, I found the outputs are all "X". (After digging into the design, I found the final output registers do not work correctly. They are all "SDFFHQX2" in tsmc18 library. The signals before these registers are correct but are incorrect after them.)

If I didn't attach .SDF, simulating .v generated correct outputs. Of course those output registers work correctly too. That's why I am suspicious about the warning messages related to .SDF file.

The script I used to dump .v and .SDF is:

; Dump SDF File
ataDumpSDF
setFormField "SDF Write" "Flatten Format" "1"
formOK "SDF Write"

; Verilog out
menuReload "astro_data_prep"
auVerilogOut
setFormField "Verilog Out" "Library Name" $DESIGN_LIB
setFormField "Verilog Out" "Cell Name" $TOP_CELL
setFormField "Verilog Out" "Verilog Out Data File" "sdm_layout.v"
setFormField "Verilog Out" "Output Bus As Individual Bits" "0"
setFormField "Verilog Out" "Reference Top NETL Cell To Output Bus" (string-append $TOP_CELL ".NETL")
formOK "Verilog Out"


Any hints are appreciated.

ncsim out.v

Hi,
OK, your problem is more to do with so called "X-poisoning" in gate level simulation. You first make sure that there are NO setup/hold violations on the output cells of type: SDFFHQX2. If there are, analyze them carefully - after all that was the whole point of doing this SDF annotated simulation.

BTW, in your previous post you showed the problem with SDFFNRX2 cell and now you are saying problem is with SDFFHQX2 cell. If that indeed is true, you don't worry abou the ncelab errors for now - focus on SDFFHQX2 cell's errors - if any.

If you are convinced that there is no timing problem, you can turn OFF timing check on these specific cells/instances. But before even going there, first make sure your setup/hold rules are met for this all the more important cell: SDFFHQX2

Good Luck
Ajeetha, CVC
www.noveldv.com
New Book: A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
https://www.systemverilog.us/

nc verilog sdf

Could you please provide more details about so-called "X-poisoning" gate-level simulation? Why "X-poisoning" shows up only when SDF information is attached?I can't get any useful help from the Internet.

I did more simulation: I removed output registers in RTL codes temporily and P&Red again. After post-simulation, I found that the output signals are still "X"s. So it has nothing to do with specific cells (I had thought SDFFHQX2). It seems to me that any final output signals would be "X" if SDF is attached with the netlist. However all intermediate signals are correct.

Thanks again for your kindly help!

ncverilog compile append

Hi eruisi,

I have the same problem as yours.

Have you got your solution yet?. If yes, can you share with me?.

Thanks.