What is the reason for the present state and the next state changing simultaneously?

HI,

I am in the proces of designing a scrambler.

When i use the testbench to check the functionality of it,it works fine when inputs are passed as with certain delays.
The test bench is like this:
initial
begin
#20 descram_en = 1'b1;
ck = 64'h649dbdbe0cf0cfcb;
#20 descram_en = 1'b0;
#20 tspayload=1'b1;
area_sel = 2'b0;
scrambler_select = 1'b1;
data_in=64'h00000000_12345678;
#20 data_in=64'h6cbfa0e5_a96ddc60;
... i continue to pass the data in the same way. the clock is generated as:
initial
clk = 1'b1;
always
# 10 clk=~clk;

The code works fine for the above input.
When the testbench is changed as below the present state and the next state change simultaneously and ultimately i get the incorrect output.
initial
begin
wait(rst);
@(posedge clk);
descram_en = 1'b1;
ck = 64'h649dbdbe0cf0cfcb;
@(posedge clk);
descram_en = 1'b0;
@(posedge clk);
tspayload=1'b1;
area_sel = 1'b0;
scrambler_select = 2'b01;
data_in=64'h00000000_12345678;
@(posedge clk);
data_in=64'h6cbfa0e5_a96ddc60;
... the clk is produced in the same module like above.
What is the reason for the present state and the next state to change simultaneously.Is the test bench correct?

regards
jesu

Re: state changes

In the second testbench, what happened to descram_en at posedge clk? In the first case, you forced it be apart while the second one seems uncertain.

Just 2 cents.

Re: state changes

Better use Non Blocking <= statement while driving the outputs w.r.t. Since it is blocking the outputs are seen on the same as on the edge it is driven.

I hope u get wht i want to say.

Re: state changes

Thanks for ur reply.The code is working properly.