Estimate gate count in Verilog?

gate count estimation 90nm

Hi,

When I design a circuit, how to estimate gate count? Is there any reference?

And is it related to the technology like 180nm or 90nm?

Thanks!
Davy

Hi,

If you happen to have Synopsys Design Compiler in-house, this might help. This example uses a 130 nm library from LSI Logic. So, yes, the library and technology matters. The example below is if Synopsys reports cell units - which it did for 130 nm LSI library.

Gate Count estimation
Things you'll need to complete this task.
1. DC area report of the design
2. Library cell unit to gates conversion factor. (This is from the ASIC vendor).

After synthesis gate count
normally, after synthesis, SCAN flops have not been inserted. So, you'll need to factor this in. Typically, the increase is 25% of noncombinational logic.

From synthesis area report, the two items that are important are
- Combinational Area (A)
- Noncombinational area (B)

1) compute estimated total gate count of design with SCAN flops by multiplying 1.25 to the Noncombinational area.
2) add result of 1 to combinational logic to get total cell area
3) convert cell area to gates by dividing result of 2 by gate factor. For LSI, it is 3.15.
4) result of 3 is gate count.

When comparing to previous design, growth percentage is determined by the following formula:

((new_gates/old_gates) - 1) x 100% = percentage increase


The equations are different for 90 nm since Synopsys area is reported in square microns - again, I believe it depends on the library. In this case, if you treated Synopsys area as cell units, your gate count would be much smaller and incorrect.

The reference is the area of 2 input Nand gate.

Usually, gate count = (total standard cell area) / (area of 2 input Nand gate).

According to above formula, it's independent from the process technology.
No matter it's 90nm or 0.13um.

joe2moon said:

The reference is the area of 2 input Nand gate.

Usually, gate count = (total standard cell area) / (area of 2 input Nand gate).

According to above formula, it's independent from the process technology.
No matter it's 90nm or 0.13um.

Click to expand...

As to "area of 2 input Nand gate", there are many different drive strength for nand gate, the area is different, in the formula, does it refer to smalles drive strength such as x1? or what? Can anybody clarify it?

Yes.
Generally speaking, 2 input Nand gate refers to Nand2 x1.
---------------------------------------------------------------------------------

a 2 input NAND gate has same area in all drive strengths

spauls said:

a 2 input NAND gate has same area in all drive strengths

Click to expand...

no, they are different, for a .5um preocess example:
MACRO ND02D1
SIZE 5.40 BY 16.20 ;
...
MACRO ND02D2
SIZE 10.80 BY 16.20 ;
...
because more drive strength need more W/L ratio of MOSFETs, when W increases. cell area will increases.