Which is better to model FSMs: Matlab or Verilog?

Hi..

I've modelled FSM in Matlab before and it works fine. I know that FSM can also be modelled in Verilog but I've never tried it before.

My question is, between Matlab and Verilog, which is a better tool to model FSMs?

Thanks =]
nikki

matlab state machine

I haven't used Matlab to do that but Verilog is a standard EDA language. You should know how to code state machines in Verilog.

difference between matlab and verilog

i think it depends on the platform u want to have ur state machine implemented on at the end

matlab and verilog hdl softwares

If you are going to implement a state machine it has to be in something like verilog. But maybe Matlab can generate the HDL from the model?

matlab by palnitkar

Hi Gliss and Salma,

Thank you for responding!


Salma,

What kind of platform is Verilog? I have tried to find out more about Verilog, like what exactly is Verilog, what are the principles and applications of Verilog but there aren't any documentation on that, as far as I can find. Does anyone know any good websites that can explain ABOUT Verilog and not HOW to use Verilog?

Gliss,

As far as I know, I don't think MATLAB can in any way generate the HDL from the model... (I think)

Thanks,
Nikki

matlab to verilog

hi,

Verilog is a hardware description language...it's used to write code that will be implemented on hardware at the end....on FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit) or CPLD (Complex Programmable Logic Device)....so, it's used to describe ur designs in software then have them on hardware... instead of using discrete components...

verilog and VHDL are two famous HDLs...verilog is more close to transistor level and it isn't strongly typed.....VHDL is more abstract and strongly typed...

State machines can be written in any HDL....some softwares give the option to draw the State machine and then generate code for it...

u can find lots of books on verilog here in the search

there is also the evita tutorial from Altera

hope that was useful,
Best Regards,
Salma

implementing fsm in matlab

Matlab is one thing and Verilog is another completely different thing.

Each of these are developed to do their specific tasks.

I know both very well. If I want to test a fsm generally, I'll use matlab. ( pure software development )

If I'm going to develope a FPGA design or a hardware I'll use verilog.

I'll always use available FSM design tools instead of writing the code directly. Matlab provides this tool ( I do not know the name but I'm sure there is such a thing ) for verilog also similar tools are available.

evita verilog how to use

Hi, nczx,

First of all, Matlab is completely different tool (actually a tool) than Verilog (it's a language). Verilog is a Hardware Description Language (HDL). There are many such languages like VHDL (it stays for Very High Speed Integrated Circuit (VHSIC) Hardware Description Language). Matlab is used for system modeling and analysis and HDLs are used for describing digital circuits. The most convenient application of the language to experiment in hardware is to use it to program CPLD (Complex Programmable Logic Devices) and FPGA (Field Programmable Gate Arrays) programmable logics chips. Main manufacturers / vendors are Xilinx (I think the best one), Altera, Lattice, etc. Go to their web sites - they are full of datasheets, whitepapers, application notes, tutorials and FREE tools for development.
For me the Verilog language is the easy one (matter of preference). I have not tryed to model state machines using Matlab, but I know Matlab can do this. I also know Matlab can "translate" some models into HDL language, but it is kind of advanced task. In general FSM synthesis with Verilog is pretty simple. As it is difficult (and long process) to describe with several words how it can be done, try this link:
www.fpga4fun.com
It is very good site with basic (and advanced too) examples, written in Verilog. This site can give you basic ideas for many things about Verilog HDL. For example, there:
https://www.fpga4fun.com/SerialInterface3.html
is an example of state machine (simple enough).
But, I think a good starting point is to run eye over the book:
"Verilog HDL: A Guide to Digital Design and Synthesis" by Samir Palnitkar
https://www.amazon.com/gp/product/0...f=pd_bbs_1/102-9357084-4568945?_encoding=UTF8
This book can be found somewhere on this site (edaboard) for free or from amazon.
Another very good book with Verilog examples is:
"Digital Design" by Morris Mano
https://www.amazon.com/gp/product/0...102-9357084-4568945?s=books&v=glance&n=283155
I think this book is also available here (edaboard).

Cheers,
uglyduck

P.S. don't forget to press "Helped me", if I helped of course

how to convert matlab to verilog hdl

Hi Salma, mami_hacky and uglyduck!

Thank you thank you thank you!!!

You have all helped me a lot.. Now I understand the difference between Matlab and Verilog and why we would choose one over the other.. =]

So let me just get this straight....

Matlab is just for testing - software development and
Verilog is to build the actual hardware... Correct?

Thanks again for your help =]

Cheers,
nikki

draw fsm matlab

yes you got it right. let me give you an example. if you know about FIR filters then you know that the main design problem is figuring out the filter coefficients for a specific purpose. firstly in MATLAB you design your FIR filter and figure out the optimum values of the filter coefficients.

then you can use those coefficients and use them in a verilog description of your filter. synthesize that verilog code and burn it on to your FPGA.

i hope that helps

Re: Matlab vs Verilog

Hi Samcheetah!

Excellent..!! Thanks for the post =]

Thanks to all those who have helped me..

Cheers,
Nikki =]

Matlab vs Verilog

In the name of God
Matlab has system modeling, control and DSP applications and verilog has digital system design applications.

Re: Matlab vs Verilog

Matlab is algorithmic analysis tool. You can only have to define the functionality of your design rather than caring for Hardware implementation. There are some tools like AccelDSP Synthesis Tool,System Generator for DSP which automatically generate Verilog or VHDL code from your matlab program.I dont know the exact details of the tools so i'll suggest you to kindly consult www.xilinx.com.

Re: Matlab vs Verilog

"As far as I know, I don't think MATLAB can in any way generate the HDL from the model... (I think)"

using MatLab SimuLink it is possible to generate the HDL...

Matlab vs Verilog

what you want to do ? just model a fsm? it will not be used in read word?

Re: Matlab vs Verilog

using matlab u can simulate ur code ,using varilog u can implemnt in real life

Matlab vs Verilog

can anyone give me a link that provide the 'perfect' tutorial for matlab and verilog??

thanx

Re: Matlab vs Verilog

matlab an vari log are two diff plateform but both are wonderful using matlab u can simulate ur aplication an using varlog (fpga) implemnt real time aplication thats it

Re: Matlab vs Verilog

As I know, there are too many EDA tools can implement FSM by different methods.
But they can be divided by two types roughly.
One is HDL coding. Another is modeling.
HDL code is like as Verilog or VHDL.
Modeling is to create FSM by graphic mode

Matlab vs Verilog

i want to know how to convert matlap code to vhdl code to implement tx for cofdm