Xilinx CoolRunner II - TIMESPEC problem

xilinx timespec

Hello, Verilog gurus,

I'm experiencing the following problem:
I try to implement a design on Xilinx CoolRunner II using ISE WebPack 7.1.i_04. The design is written in Verilog. The design uses 1.8432MHz clock which is internally divided when needed to ~20Hz. Behavioral simulation is passed OK. But when I try to run "Implement design" from "Processes for source..." I get the following error (warning actually) messages:
=============================
Started process "Generate Timing".

Release 7.1.04i - Timing Report Generator H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for
analysis.
WARNING:Cpld:310 - Cannot apply TIMESPEC TS1000 =
PERIODERIOD_SPEED/PULSE/q10_MC.Q:0.000 nS because of one of the following:
(a) a signal name was not found; (b) a signal was removed or renamed due to
optimization; (c) there is no path between the FROM node and TO node in the
TIMESPEC.
WARNING:Cpld:310 - Cannot apply TIMESPEC TS1001 =
PERIODERIOD_SPEED/PULSE/q1_MC.Q:0.000 nS because of one of the following:
(a) a signal name was not found; (b) a signal was removed or renamed due to
optimization; (c) there is no path between the FROM node and TO node in the
TIMESPEC.
WARNING:Cpld:310 - Cannot apply TIMESPEC TS1002 =
PERIODERIOD_SPEED/PULSE/q2_MC.Q:0.000 nS because of one of the following:
(a) a signal name was not found; (b) a signal was removed or renamed due to
optimization; (c) there is no path between the FROM node and TO node in the
TIMESPEC.
WARNING:Cpld:310 - Cannot apply TIMESPEC TS1003 =
PERIODERIOD_SPEED/PULSE/q3_MC.Q:0.000 nS because of one of the following:
(a) a signal name was not found; (b) a signal was removed or renamed due to
optimization; (c) there is no path between the FROM node and TO node in the
TIMESPEC.
WARNING:Cpld:310 - Cannot apply TIMESPEC TS1004 =
PERIODERIOD_SPEED/PULSE/q4_MC.Q:0.000 nS because of one of the following:
(a) a signal name was not found; (b) a signal was removed or renamed due to
optimization; (c) there is no path between the FROM node and TO node in the
TIMESPEC.
WARNING:Cpld:310 - Cannot apply TIMESPEC TS1005 =
PERIODERIOD_SPEED/PULSE/q5_MC.Q:0.000 nS because of one of the following:
(a) a signal name was not found; (b) a signal was removed or renamed due to
optimization; (c) there is no path between the FROM node and TO node in the
TIMESPEC.
WARNING:Cpld:310 - Cannot apply TIMESPEC TS1006 =
PERIODERIOD_SPEED/PULSE/q6_MC.Q:0.000 nS because of one of the following:
(a) a signal name was not found; (b) a signal was removed or renamed due to
optimization; (c) there is no path between the FROM node and TO node in the
TIMESPEC.
WARNING:Cpld:310 - Cannot apply TIMESPEC TS1007 =
PERIODERIOD_SPEED/PULSE/q7_MC.Q:0.000 nS because of one of the following:
(a) a signal name was not found; (b) a signal was removed or renamed due to
optimization; (c) there is no path between the FROM node and TO node in the
TIMESPEC.
WARNING:Cpld:310 - Cannot apply TIMESPEC TS1008 =
PERIODERIOD_SPEED/PULSE/q8_MC.Q:0.000 nS because of one of the following:
(a) a signal name was not found; (b) a signal was removed or renamed due to
optimization; (c) there is no path between the FROM node and TO node in the
TIMESPEC.
WARNING:Cpld:310 - Cannot apply TIMESPEC TS1009 =
PERIODERIOD_SPEED/PULSE/q9_MC.Q:0.000 nS because of one of the following:
(a) a signal name was not found; (b) a signal was removed or renamed due to
optimization; (c) there is no path between the FROM node and TO node in the
TIMESPEC.
Path tracing .........
The number of paths traced: 905.

.....
The number of paths traced: 1811.

Checking for asynchronous logic...
Generating TA GUI report ...
Generating detailed paths report ...

c:\xilinx\work\robot/SpeedMesTop_html/tim/timing_report.htm has been created.
=============================

I have written a testbench in Verilog. I have assigned all the pins I will use. No other constraints. I suppose I have to make some "Time constraints", but...
Explanations, given by the ISE are not very meaningfull to me. Please, help me. Where I'm wrong? My other smaller designs have been implemented this way - no special constraints - just the pin assignment.

When actually timing constraints are needed?
How to use them (just the basic stuff and the most common)?
And why I cannot perform Post-Fit Simulation using such a simple testbench? I miss something essential and eventually very simple, but don't know what to do.

Please, I desperately need your help.

ise false path timespec

Hi,
First of all apply the clock constraints on ur design . No other constraints are needed if u r not specific abt the performance, cross clock, and pad delays.
also try to serach the net which is described in the error.

I think clock constrains will be enough.

coolrunner ii troubleshoot

Hi, bansalr,

Thank you for your reply
I tryed to put some timing constraints and the error is gone. It worked
But, since I'm relatively new to Verilog (and even to digital electronics in some aspects) I am a little bit confused - there are so many settings... clock to pad, pad to pad, on rising clock edge, on falling clock edge and so on. What are the most important ? I should be able to uderstand at least the basic constructs. Could you point me to the most essential constraints. Those, explained by Xilinx manuals are too complex (I mean, since all constraints are described there) - I don't know from where to begin - kind of Step-by-Step for Dummies...
Any book, link, whatever... on this topic ?

Cheers,
uglyduck

xilinx timing path cross-clock asynchronous

Hi,
U can start with the clock constraints then slowly u can add the other constraints.
Try to get sample script.
xilinx u will find constraint doc where u can find all the constraints.
1. After clock constrains u can add PAD locking constraints.
2. Add Cross clock false path constraints
3. Add OFFSET IN and OFFSET OUT for critical signals on FPGA PAD.
4. u Can add MAX delay constraints for Combinationsl path