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gated clock vs CE(Clock Enable) for LOW POwer Design

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eda_wiz

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hi ,
gated clock vs CE(Clock Enable) for LOW POwer Design.

which one is good for a low power design.
comments please.
Also please mention other poupular low power methodologies


tnx
 

Gated clock will introduce lots og problem like signal racing. It need a very careful design. Clock enable is a more common on low power deisgn.
 

Gated Clock:
Pro - Less power (about ~40% of Flip-Flop power is dissipated on the Clock input stage).
Con - It is NOT DFT (Design For Test) compliant, and not so methodological.


Clock Enable:
Pro - DFT compliant, STA compliant
Con - Even if clock is disabled, power IS dissipated at Flip-Flop input stage !

Other Low-Power methodologies:
1. Use ripple counters instead of synchronous counters
2. Architect your RAMs data width using LESS column/rows amplifiers.
3. Use pre layout floor-plan tactics to reduce length of metal/poly interconnects (to reduce RC and capacitive loading).
4. As many as possible clock-islands, and as lesser operating frequency(ies) as you can.
 
I have started in the analog domain. So I would prefer clock enable. The difference is simply that the CLKI->CLKO delay is now predictable and not distort by the P&R. Nevertheless the input has to driven by the clock driver. So the reduction is 50-90%. If clock enable is integrated into the clock tree there could be a nearly a perfect 100% reduction with low skew. But it is a more analog technique.
 

clarify Clock enable & Gated Clock

As I know, in most ASIC libraries, the clock enable pin of a flip-flop is implemented by putting a MUX in front of the flip-flop D input, when CE is enabled, new data will be select, otherwise, Q will be wired to D, so the old data will be retained. So actually, Clock Enable has nothing to do with reducing the power. If you want save power, you should use clock gating techniques, which indeed disable the clock of the flip-flops. There are many ways to do so, but what ever you use, the following guidelines should be followed:
1. avoid clock glitch
2. avoid clip the clock active phase
3. reduce the impact on DFT coverage

More details, please refer to synopsys power products manuals, like "Power Compiler User's Manual".
 

Clock gating technics are very common today. All ASIC libraries contain clock gater cells used for that purpose. It's sure that you must be careful when using them but all mobile system need these clock gater cells to reduce the power comsumption. It's the only way to obtain a good optimization.
 

Hi, rod_wu:

I believed farmerwang had posted your answer.
.....the clock enable pin of a flip-flop is implemented by putting a MUX in front of the flip-flop D input, when CE is enabled, new data will be select, otherwise, Q will be wired to D, so the old data will be retained. ....

Let me put more lines here. In CE, clock still kept switching on the clk input of all the flops, but the data behind the CE gate(s) kept constant, till the CE was released. The power kept burning on the clock network, but the rest of the ckt just needed to worry about the leakage.
 

Hi,

As far as i know, Cadence had proposed some low power design flow in their backend tool which will modify the final gate-level netlist. I had heard that 30% power reduction is achieved thru real tapeout. The method Cadence tool uses is based on gated-clock technique. Could somebody who is familiar with Cadence tool provide his experience with us ??

Thanks in advance : )
 

kwkam said:
Gated clock will introduce lots of problems like signal racing.
Click to expand...

Could you please provide more detail explanation why Gated Clock may introduce signals racing? As far as I understand, insertion of the gated clock is done in the boundaries of the pre-defined skew. So, why the signals should be raced?

Is it harder to build a Clock Tree when a gated clock was inserted during Logic Synthesis?

- - - Updated - - -

While insertion of the Gated Clock, should the Enable signals to the flops be preserved?
 

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