davyzhu
Advanced Member level 1
Hi all,
I am new to SystemVerilog.
My friend told me TYPE1 can be compiled and TYPE2 cannot be compiled, is it right?
BTW, I use cadence tools.
Best regards,
Davy
I am new to SystemVerilog.
My friend told me TYPE1 can be compiled and TYPE2 cannot be compiled, is it right?
BTW, I use cadence tools.
Code:
covergroup cg0@(negedge CLK);
one_sig: coverpoint one_sig
{
//TYPE1
bins a = {1} iff(vaild )
//TYPE2
bins a = {1} iff(vaild ==2);
... ...
}
Best regards,
Davy