a question on Fractional-n pll.

fractional pll

what is the max phase error of a fractional pll?

ex: a pll with a mash 111 delta-sigma modulator.
the divider has 8 output level: 10,11,12,... 17.
Pll reference clk is 10MHz.
What will be the maximum phase error between the PFD input(ref and div_out)?

thanks.

fractional n pll

Hi

Please note that the max. phase error of Frac-N depends on many factors, not just the divider. I think your DAC will effect the phase error by a large value. Even noise will change the error.

If you have all the details of your PLL, the best option is to make some model (Matlab or even Spreadsheet) to get the result.

Doing it manually is really difficult. You'll need to solve some simultaneous discrete time equations.

BTW, why are you planning for an eight level divider. I think it'll increase your period jitter as compared to fewer number of levels. What do you say?

pll sdm clock

advaita said:

BTW, why are you planning for an eight level dac. I think it'll increase your period jitter as compared to fewer number of levels. What do you say?

Click to expand...

I don't see any plans of using a dac at all in the original post, only a digital MASH sigma delta modulator (sdm) controlling a mulimodulus divider.

But back to the question; I am not really certain what would be the correct answer, but I could come with some inputs.
First of all it is important to realise that a fractional PLL (mash111) is newer really locked when you look at it in the time domain. That is the frequency is constantly jumping up and down with an average identical to your programmed frequency, so looking for a phase error might be some troublesome.
But you usually interprets the output from the first accumulator (for a 1st order sdm) as the phase error vs. time. So looking at this your phase error constantly rotates from zero to 2pi with the resolution of your fractional input (eg 1000 / 2^20 for a 20 bit accumulator).
If you have a 2nd order sdm the output of the second accumulator represents the integrated phase error, so you would have to make 1 differentiation of the output to get the phase error and 2 differentiations for a 3rd order sdm, and so forth.
It is a good lesson to look at these outputs and looking for periodicity (ie one possible origin for spurs) and notice how the phase error is 'randomized' as the sdm order is increased.

sdm in pll

Thank advaita and rfasic.
thank u for ur reply.

There is no dac in system acturally.
Eigth output levels are possible multi modulus divider ratio.

rfasic gives a good method to analysize the problem.
I will run some simulations to verify my thoughts.

Thanks.

output of multi-modulus divider

Hi

By mistake I mentioned eight level dac. I meant 8 level divider

Here's an example why I think a higher mod divider will lead to a higher jitter:
Suppose you need frequency mult. by 11.2 and you use use this eight level divider so you'll get a division of output clock by 17 after few reference cycles, i.e, you'll get about "6 Output clock equivalent" phase error at the PFD which will then kick the VCO strongly leading to a high jitter. May be this can be fixed by suitably choosing the loop filter.
Can you please share what is the advantage of using this eight-modulus divider? Is it that it pushes more noise to higher frequency?

rfasic,

I thought that the sig-delta is used just for randomization of division factor but never thought of it the way you mentioned.
I am sorry I could not understand it much. Can you please send some link which explains your point of view.

Thanks