Metal layers used for power routing

hi,

i have read somewhere that lowest metal layer for eg: Metal 1 is used for power routing, but in a tutorial for SoC Encounter they h ave given that Metal 5-6 are used for power and ground straps and rings..... y is that so??????


please reply soon.


thanks in advance,
Prasad

No Prasad the lowest metal is used for std cell placement. Normally the highest metal layers are used for the power routing bcoz the resistance associated will be less for the top layers

so the highest metal layers i.e 6 in 0.18 um tech would have least resistance??
while metal 1 have highest resistance ?????is that what you want to say????


but till now we were using Metal 1 for Vdd and Vss ?


thanks,
Prasad

hi

Metal 5 and 6 will have larger width and less sheet resitanance when compare to lower metal..

So higher metal layers are used as ring and straps.. it willbe easier for carrying VDD and VSS downto lower metals.

Metal 1 is lowest metal and it is used for routing rail connecting vss and vdd to standard cells


Regards
Shankar

shankarmit said:

hi

Metal 5 and 6 will have larger width and less sheet resitanance when compare to lower metal..

So higher metal layers are used as ring and straps.. it willbe easier for carrying VDD and VSS downto lower metals.

Metal 1 is lowest metal and it is used for routing rail connecting vss and vdd to standard cells


Regards
Shankar

Click to expand...

So comparing one metal-6 and one metal-1 paths with the same width results to metal 1 having lower resistance. So what is your point here??

thats what the thing as in my technology file all metals 1 to 6 has same width , is that wrong then???????

i am using 0.18um TSMC technology.


thanks,
Prasad

p_shinde said:

thats what the thing as in my technology file all metals 1 to 6 has same width , is that wrong then???????

i am using 0.18um TSMC technology.


thanks,
Prasad

Click to expand...

I dont know the tools you are using and how they work. In generall the metal width does not say nothing by it self. The metal width is a design rule of the process you are using. So if you are creating a layout you may create a metal path with whatever width but when you will go through a DRC it will produce an error if it violates the design rules of the process.

Regarding the use of metal layer for power supply:
In theory the M1 M2 are the best for global power supplies because of the lower resistance. The only rule that you can find (for example in a layout technique book), regarding the metal layer is : dont use many layer transitions, go just from M1 to M2 and back. In reallity most processes have specialized layers for power.

PS: I am not an expert in this field. The above is just from what i have encountered in my work. :|

clcok and reset are at high layers

- We often use the highest layer for Power and clock-routing ( metal7 & metal8) , In some case using the lower metal to avoid IR - drop violation .
- About layer1 , This layer only can use for very short routing ( jog-route) , between two or more cell-pin .

So comparing one metal-6 and one metal-1 paths with the same width results to metal 1 having lower resistance. So what is your point here??


so u can have larger width metal4 and metal5 than metal1 and can carry voltage to the entire chipand less IR drop..
Do u understand..

When using higher metals it s easy to deliver the power downwards to the standard cells


Regards
Shankar

In the project i am carrying out,M1,M2 & M3 have the same sheet resistance.That means that all the 3 metals are having the same resistance.Then where is the question of M3 having the least resistance and M1 having maximum resistance?

What effect will this have on the supply?

This is an analog project.