xfpgas
Junior Member level 2
Xilinx Virtex Questions
I see these parameters listed in Virtex Datasheet. VCCINT, VCCO, VREF,VIN. I dont have a good EE background (I am a CE ). However I really want to understand the electrical part of the FPGA. Please pardon me if i sound ignorant..
I know the Virtex CHIP requires a 2.5V to power up , or the 2.5V is the core voltage.
1) What does the term CORE Voltage really mean? I mean the Core Voltage is 2.5V, but how can I have IOs on the chip that tolerate 5V, how is this different from the core? How does Xilinx Do it?
2) Why would an engineer wanto look at these parameters VCCINT, VCCO, VREF, VIN and any other I might have missed? What do they mean?
3) I understand that in Virtex each bank can be configured independtly in terms of the IO standard ( LVTTL, PCI etc). I also understand that depending on the IO standard of the Bank, each bank would need a VREF. Am I correct? But I really dont understand how this works.
4)Also, what are the possible scenarios in which you can fry a Virtex FPGA ( or any other FPGA) on a board, specifically electrical issues.
5)If a Virtex is fried, what really happens ..imean the electrical stuff on the CHIP. I want to understand the process.
Please feel free to treat me as very ignorant of some basic EE stuff when you answer the questions
TIA,
Kode
I see these parameters listed in Virtex Datasheet. VCCINT, VCCO, VREF,VIN. I dont have a good EE background (I am a CE ). However I really want to understand the electrical part of the FPGA. Please pardon me if i sound ignorant..
I know the Virtex CHIP requires a 2.5V to power up , or the 2.5V is the core voltage.
1) What does the term CORE Voltage really mean? I mean the Core Voltage is 2.5V, but how can I have IOs on the chip that tolerate 5V, how is this different from the core? How does Xilinx Do it?
2) Why would an engineer wanto look at these parameters VCCINT, VCCO, VREF, VIN and any other I might have missed? What do they mean?
3) I understand that in Virtex each bank can be configured independtly in terms of the IO standard ( LVTTL, PCI etc). I also understand that depending on the IO standard of the Bank, each bank would need a VREF. Am I correct? But I really dont understand how this works.
4)Also, what are the possible scenarios in which you can fry a Virtex FPGA ( or any other FPGA) on a board, specifically electrical issues.
5)If a Virtex is fried, what really happens ..imean the electrical stuff on the CHIP. I want to understand the process.
Please feel free to treat me as very ignorant of some basic EE stuff when you answer the questions
TIA,
Kode