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Question about analyzing gate delays

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beejan

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gate delay

Hi All,

I have a basic doubt in gate delays. When we analyze the gate delay of and gate in 90nm , 65nm and 45nm technology which one is more. Pl. give me proper exlanation and justification for the same
 

Re: gate delay

gate delay usually depends upon 5 parameters
(1) Input Transition
(2) Output load
(3) Process
(4) Voltage
(5) Temperature

usually high technology lib has low gate delay.
 

    B

    beejan

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Re: gate delay

i lowest process that 45nm will have lowest gate delay..

because if you know about device models you can undestand why lower process has lower delays..

the distance travelled by electron from source and drain becomes less in lower process..

its all device physics..

Regards
Shankar
SEE analog forum u can get accurate result...
 

Re: gate delay

Finer the geometery, smaller are the gate delays. But yes a gate delay may depend upon a number of factors. Such as voltage, output load, input slope, temperature.
As the geometery shrinks, the output load on a gate is likely to shrink, which will help reduce gate delays. The channel lengths are also shorter, so less delay again. But lower voltage could cause more delay.
The net effect is however less propogation delays for finer geometeries.
Kr,
Aviral Mittal
 

    B

    beejan

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Re: gate delay

In order to justify the concept, I calculated the AND gate delays (50%) for 130,90,65 and 45nm tech... in eldo. The result is given below , but this values are not correlating properly. Could you please cpmment on it ?

130nm 53.7ps
90 52.6ns
65 81.05ps
45 122ps


avimit said:
Finer the geometery, smaller are the gate delays. But yes a gate delay may depend upon a number of factors. Such as voltage, output load, input slope, temperature.
As the geometery shrinks, the output load on a gate is likely to shrink, which will help reduce gate delays. The channel lengths are also shorter, so less delay again. But lower voltage could cause more delay.
The net effect is however less propogation delays for finer geometeries.
Kr,
Aviral Mittal
Click to expand...
 

Re: gate delay

I guess you have used same load for the simulations. Also pls give detailed simulation specifications of your simulation env. such as VDD, slope, load etc. And most important is where did you get the simulation models from?
Kr,
Avi
 

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