18-bit 1024 locations RAM in Spartan-3

xapp464

Hello all,
I want to know how I can define a Block RAM memory of more than 16-bit, that must have 1024 locations.
I have already the templates to define a Block RAM for 16 bits of data, including 2 bits of parity, this is a dual port memory, the template I downloaded from xapp464.zip from Xilinx documentation.
This document xapp464.pdf, also says that if one needs a deeper memory, the only thing that should be done, is cascade columns of RAM from the FPGA.
Does somebody knows how to do this?
In a few word, what i need is to implement a dual port RAM for more than 16 bits of data (not including parity bits), and 1024 locations.

Currently, with instantiations, I am defining a RAMB_18_18, which is a 1024-location 16-bit wide RAM, and two parity bits. I need a deeper memory.

Thanks and Regards,

1024*16 bits sram

Simply put 2 or more in parallel.

You tie the address, control, ... everything together, except for the data.

You can separate write-enables too, if you want to be able to write only to one of the 16-bits word. So, for example, if you want 32 bits wide, but wish to be able to write to only the low 16-bits or high 16-bits at a time, then you can assert only one of the write enables.

Note that there is only one write-enable per block, so, if, for some reason, you need byte granularity, then you need to multiple 2048x8 RAMB.

O.K. That must help. Thanks Big Boy.

Yes, just like Big Boy said, that will do.
However, if you'r interested in some other mechanisms for this, you can instantiate two 36_36 blocks and link'em together. All what you need to do is to manipulate the address bus as to map it accordingly to both blocks. Very easy stuff. Concatentate the most significant bit to the original address bus after supressing the least significant. Fair and square.
Cheers.