[Question] Can this Class-AB output stage work?

Hi,

Many OpAmp designs and text books have this kind of class AB output stage with feed forward biasing.

"The trick in designing a rail-to-rail output is in the biasing of the two output transistors. You want a small but well-controlled idle current to minimize any uneven behavior as the output signal is switched from one transistor to the other. In this circuit there are eight transistors whose only job is to set
this idle current." --- Hans Camenzind, Designing Analog Chips.

I want to use this struture, but I have trouble in my simulation. The problem is one of the two transistor, M3 and M7, conducts most of the tail current that the other one is forced to turn off. Actually the NMOS, M3, tends to completely turn on and forced its Vds to be very small (0.2V because ron is small), that the PMOS, M7, just can not get the proper biasing and is turned off.

I tried to tuned the circuit and found that the sizing of transistors are sensitive, it is not easy to tune. So that I doubt how robust this circuit is. (I believe IC design is about matching not fine tuning the size). Is there trick to tune this circuit? How this circuit work? Thanks.

I have the same question too! at the same time, I do not know how to confirm the w/l of these MOS transistors

anyone knows? Thanks.

This is absolutely normal...

The problem is that you are simulating this circuit OPEN LOOP.

The problem with open loop simulation is that small discrepancies between the currents of the output transistors will cause one of them to turn off ( this is a very common problem, and for this same reason CMFB is used in fully differential Amp's )

I think you need to close the loop. Use your amplifier ( or just a behavioral model of an amplifier ), connect it to this output stage then close the loop.

I believe it will work then...Tell me if it doesn't

Regards

elbadry said:

This is absolutely normal...

The problem is that you are simulating this circuit OPEN LOOP.

The problem with open loop simulation is that small discrepancies between the currents of the output transistors will cause one of them to turn off ( this is a very common problem, and for this same reason CMFB is used in fully differential Amp's )

I think you need to close the loop. Use your amplifier ( or just a behavioral model of an amplifier ), connect it to this output stage then close the loop.

I believe it will work then...Tell me if it doesn't

Regards

Click to expand...

Thanks a lot. Yes, it works. But the question remains. Currents of those two transistors, M3 and M7, are not easy to control. It is very likely that one of them conduct most current. Is it necessay to keep the currents of those two transistors close to each other?

As far as I understand, the currents would be equal only if the output is at mid-supply. otherwise, they should be different to drive the output stage

elbadry said:

As far as I understand, the currents would be equal only if the output is at mid-supply. otherwise, they should be different to drive the output stage

Click to expand...

even the output is half the supply voltage, the two currents are sensitive to the transistor parameters, process and temperature. My question is, what is the point to make them equal?

I think the point is that M1, M2, M3 and M4 form a translinear loop which is characterized by:

Vgs1 + Vgs2 = Vgs3 + Vgs4

Hence if Vgs1,2 = Vgs3 ---> Vgs4 = Vgs1 ( as if the output transistor is having a mirror current from M1 )

As you need the NMOS and PMOS currents (of the output ) to be equal, you have to make currents in M3,M7 equal to those in the diode connected NMOS and PMOS branches.


I think that if in the end you get the current you want in the output branch, then you do not have to bother about the two current being equal.

i.e. In the end, you want the output current = k*current in diode stack

where K is a mirroring factor

yolande_yj said:

elbadry said:

As far as I understand, the currents would be equal only if the output is at mid-supply. otherwise, they should be different to drive the output stage

Click to expand...

even the output is half the supply voltage, the two currents are sensitive to the transistor parameters, process and temperature. My question is, what is the point to make them equal?

Click to expand...

whether the current is equal don't depend on the output at mid-supply, it should depend on whether the output tranisitor M4 and M8 have same output current, in other word, whether the output has resistor loading.

elbadry said:

I think the point is that M1, M2, M3 and M4 form a translinear loop which is characterized by:

Vgs1 + Vgs2 = Vgs3 + Vgs4

Hence if Vgs1,2 = Vgs3 ---> Vgs4 = Vgs1 ( as if the output transistor is having a mirror current from M1 )

As you need the NMOS and PMOS currents (of the output ) to be equal, you have to make currents in M3,M7 equal to those in the diode connected NMOS and PMOS branches.


I think that if in the end you get the current you want in the output branch, then you do not have to bother about the two current being equal.

i.e. In the end, you want the output current = k*current in diode stack

where K is a mirroring factor

Click to expand...

Here is what I find out:

The idea of those translinear loops, M1 to M4 and M5 to M8, is to give the two output transistors "small but well control idle current to minimize any uneven behavior as the output signal is switched from one transistor to the other" [1]. However, according to my simulation, the idle current is hardly well controled. I cann't see any relation between the output idle current and the two 5uA current source.

Actually the idle current is controled by the gate voltages of both M8 and M4, these two voltages are not really well controled by M3 and M7 because the current of M3 and M7 is not well defined. If their currents are fixed to half of the tail current, then the Vgs of both M3 and M7 are defined, but since the drain voltages of M9 and M10 are very losse, their final value, Vin1 and Vin2, are controled by the strong feedback loop. I would say M3 and M7 do have some contribution of fixing Vin1 and Vin2, but their effect are not very strong. In fact, the currents of M3 and M7 are controled by Vin1 and Vin2, not the other way round. Thus the result is, currents of M3 and M7 are very unlikely to be equal. For most cases, one of them conducts most current and the other one operates in sub-threshold--it is dead!

To tune the currents of M3 and M7, we can tune the size of the two output transistors M4 and M8 because it is the feed back loop fixs their current (M3 and M7) assuming that their gate voltages are properly biased. Let say the current of M3 is much larger than that of M7, then reduce the W/L of M4 (to raise Vin2) or increase W/L of M8 (to raise Vin1). This is very effective and you can also tune the output idle current at the same time.

The point of M3 and M7 here should be: to give the two output transistors small idle current to minimize any uneven behavior as the output signal is switched from one transistor to the other. M3 and M7 are not much better than a simple resistor I think (if we can make the resistor small). How to control this idle current? I think we have to tune the size of the output transistors. Again, not much control on it.

[1] Hans Camenzind, "Designing Analog Chips"
**broken link removed**

I have 2 questions :

1 : I saw a circuit in which W/L of M8 is 5 times that of M4 .
So as the Iq of M4 and M8 is equal , and KPn≈3KPp ,
the Gmnmos will not equal to Gmpmos . When Vin1 has
the postive and negtive changes , the output current
will not equal . Am I right ?
2: I think the current in M3 and M7 should not be equal
,but their Gm should be equal .
My reason is when has some ac current from Vin , the voltage
change in Vin1 will be ΔI*Gm3 , in Vin will be ΔI*Gm7 ,
So , if Gm is equal , the ΔV will be equal . Am I right ?

Can anyone tell me the operation theory of this circuit?
I am a starter.
thanks!