Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

one_hot and zero_one_hot

Status
Not open for further replies.
W

wangkl

Member level 3
Member level 3
Joined
Feb 17, 2005
Messages
67
Helped
4
Reputation
8
Reaction score
1
Trophy points
1,288
Location
FSL
Activity points
1,829
zero_one_hot

What's the difference between these two concepts: one_hot and zero_one_hot?
I'm a little bit confused.
 

what does one_hot pragma do

Hint:
Use google to find zero_one_hot and read the first record.
 

zero one dirty.com

It's a pdf file and without any explaination.
I guess google is characterized for different location.

Actually, I met problem while I read Cadence LEC document:

ADD PIN CONSTRAINTS

ONE_Hot Specifies that only one of the pins can have a high value.
ONE_Cold Specifies that only one of the pins can have a low value.
ZERO_ONE_Hot All pins can have a low value, but only one can have a high value.
ZERO_ONE_Cold All pins can have a high value, but only one can have a low value.
 

example of one hot constraints in cadence lec

OK.

I will post what's in the pdf:

The definition of one-hot as given here ("in which only one
signal in the collection is active at a given time") is useful one,
but is not the normal definition of one-hot. (In OVL, the Open
Verification Library, this check is known as zero_one_hot.)
This will cause confusion.

Change the definition of ONE_HOT to "...in
which one and only one signal in the collection
is active at a given time", and add a second
attribute ZERO_ONE_HOT with the definition
"...in which at most one signal in the collection
is active at a given time". Similarly for
ONE_COLD and ONES_ONE_COLD.


Will u be satisfied now ? :)
 

    W

    wangkl

    Points: 2
    Helpful Answer Positive Rating
zero one dirty

So in the other word:

One_hot: at least 1, only 1 and at most 1 "one" is active in a given time.

zero_one_hot: at least 0, and at most 1 "one" is active in a given time.

Is my understanding correct? Thanks!
 

can u explain for one cold with one simple example
 

one hot:

only following states is available
state[2:0] = 3'b001;
state[2:0] = 3'b010;
state[2:0] = 3'b100;


zero one hot:

only following states is available
state[2:0] = 3'b001;
state[2:0] = 3'b010;
state[2:0] = 3'b100;
state[2:0] = 3'b000;

one cold:

only following states is available
state[2:0] = ~3'b001;
state[2:0] = ~3'b010;
state[2:0] = ~3'b100;


zero one cold:

only following states is available
state[2:0] = ~3'b001;
state[2:0] = ~3'b010;
state[2:0] = ~3'b100;
state[2:0] = ~3'b000;
 

thanks
but how synthesis tool will understand this condition
whether we have to set any pragma for this conditions?
 

thanks.i usually use one-hot.could you give me the difference when we synthesis one-hot and zero-one-hot?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top