VHDL & verilog & systemC

please i want to know the main difference between VHDL & verilog & systemC
in points


--
alieeldin

verilog
*widely used
*easy to code
*lot many tools

VHDL
*not widely used
*strict coding structure
*few tools
*easier to debug

this is my opinion

-Verilog
1. Widely used in North America, Japan
2. Difficult to debug, badly-typed
3. Smoother learning curve
4. Origins from C
5. Mediocre support for CPLDs,FPGAs

- VHDL
1. Widely used in Europe, rest of the world
2. Easier to debug, nicely-typed
3. Steeper learning curve
4. Origins from ADA
5. Much better support for CPLDs,FPGAs

in fact, VHDL is supported by tools as well as verilog, and easy to learn.

VHDL, VERILOG Are Similar In That They Are More Hardware Oriented.

C Based Languages Are More Software Oriented.

--> The Main Different Is Parallel Processing Handling.

In VHDL, VERILOG Parallel Processing Is Native. Serial Processing Approach
Is Not Efficient (Using Gigantic State Machines Instead Simple Coding In C)

In C - Parallel Processing Is Foreign Concept.

I Think VHDL Is Not Very Efficient Language, Since It Need Very Specific Syn taxes.
And Uses A lot Of Prefixes, Suffixes.

Also It Is A Very Clumsy Simulation Language, And Is Not Recommended For Big Designs.

***VHDL, VERILOG Are Similar In That They Are More Hardware Oriented.

***ERILOG is very much easier then vhdl.

FOR both VHDL & VERYLOG designer need to know other longuage for checking there functionality for this designer have to write the testbench in other language like c,c++.

*** In a systemC designer has no need to know all this they can stick with systemc for any module in systemC they may write testbench in systemC only.

***in a systemC u can export ur file in VC++, & compile & simulate that module.

Verilog is easier to learn in my opinion.

i agree, verilog is really easy to learn if you have some experience in C. i tried to learn VHDL but then i got bored and i decided to polish my verilog skills. i believe that was a wise decision

I don't know about the rest of the world, but in the US you are expected to know both Verilog and VHDL.

Verilog is probably used more in the industry, VHDL more in research as when I go to career fair, company usually only asked if I know Verilog.

In my opinion , Verilog for modules and VHDL for system flexiable.

I wish not to divulge into which language is easiier / better / faster etc.
I have used all the 3 languages and I can summarise as

VHDL : this is a hardware descriptive language , was one of the eariliest follows highly descriptive languge and very strictly adrehers to hardware description . Harder to code but once you get the code compliling you genrally don't see much of a synthesis / simulation mismatch. Major disadvantage most synthesis tools don't give out vhdl netlist , if you intend to do netlist validation/simulation.

verilog : syntax is similar to that of 'c' programming language hence most people find it easier to code in this language. But BAD CODING STYLE can cause race condition/ and simulation and synthesis mismatches. But great advantage is that doing post synthesis net list valdiaion is not much of an effort since you can obtain a veilog netlist from your synthesis tool

SystemC : All along verilog / vhdl was the language that was used to verify the design . But with time the designs started getting complex and need was felt to verify at a higher level of abstraction this is where the HVL ( hardware verification languages) came into picture. SystemC is based on c++ infact it is only a c++ library that can be used to model hardware. Major disadvantage of this that there is not a lot of support if you want for synthesis in systemc by any vendor and so it is still majorlly used only for verifiacation.

And my experice with these languages is that they are difficult onlly to begin with but not so tough that you should not put effort into them. I hope this thread does not end up with a discussion on what is superior .

semiconductorman said:

I hope this thread does not end up with a discussion on what is superior .

Click to expand...

agree with it...

in my opinion... i think it is quite hard to learn both the HDLs (VHDL & verilog HDL)... they will make u confuse and unable to master it....

i prefer to stick with one and master it...

anyway... in industry, mostly verilog is used... i dunno y... i stick wth my VHDL

regards,
sp

Well, I know both languages VHDL and Verilog. Personally I like Verilog more and I think its easier to learn.