How to add analog Verilog-A block in ADS

Hi,

I want to know steps to add an analog block described in Verilog-A to 'A'DS..

I am assumed to have the verilog-A model written in a text file, and have verilog-A design kit installed,

I will give 100 points as a reward for that,
Thanks alot in advance,
Ahmad,

verilog-a ads tutorial

ahmad_abdulghany said:

Hi,

I want to know steps to add an analog block described in Verilog-A to 'A'DS..

I am assumed to have the verilog-A model written in a text file, and have verilog-A design kit installed,

I will give 100 points as a reward for that,
Thanks alot in advance,
Ahmad,

Click to expand...

http://eesof.tm.agilent.com/docs/rfdedoc2005A/pdf/rfdeveriloga.pdf
**broken link removed**
http://eesof.tm.agilent.com/docs/adsdoc2004A/veriloga/index.html

These are tutorials on how to use Verilog-A in ADS (different versions of the same tutorial). Hope this helps..

Bharath

verilog a file

I am very happy!!

Finally, someone replied?! Alhamdulillah,

But.. I have these tutorials before, however I couldn't add a verilog block rather than that are already in Verilog-A library,

I want to add different stand alone blocks, for example, I want to discribe the behaviour of a PFD and charge pump .. and got a block like that in picture below..

How can I make that block (not asking for the code)? and how to make input and output ports to it??

This is the problem...

I want to know steps

Click to expand...

Anyway, I added 20 points to you
Thank you, and waiting for more help
Ahmad,

verilog a file ads

Hi

You should write ael component definition...
And verilogA based component is working

I have upload example for You

AEL manual (in ADS help) helps to understand "creat_item"

Regards

verilog a tutorial ads

Grig said:

Hi

You should write ael component definition...
And verilogA based component is working

I have upload example for You

AEL manual (in @DS help) helps to understand "creat_item"

Regards

Click to expand...

I did unarchieve the zap file you attached, and found a VCO like that in System-PLL components library but with different parameters, and i don't know how to make it,
I post to Agilent support online, and they replied with almost the same as you said, but i couldn't fully understand how to creat the block carrying the VerilogA model..

I could build a user compiled model, and edit its pinout..

But it's still not clear!! I tried to understand how to build the model via ael language, but i found that manual is difficult to understand, and i think it needs some C programming skills, isn't it?

Anyway, i appreciate your help, and i gave you 75 points + pressing the helped me button, but want you to know that i still didn't solve the problem

My aim isn't to creat a VCO block, but to be able to add a Verilog-A block with in/out ports for anyother component, VCO was just an example to illustrate my problem..
If you can state steps to me 1, 2, 3, ... It will be kind of you, but don't tell me to read the manual again.

BTW, I sent a mail to Agilent support online, and they replied with almost the same reply as you said.. they told me to read manual of "creating a user complied model" ...

I'm waiting for more help to solve the same problem..

Ahmad,

verilog a ads tutorial

OK

1.Write verilogA module. I have implement "funy_module" in "vco_fun.va file"
2.Open "vco_fun.ael" file using text editor (wordpad is good choice);
3.Use "creat_item......" block from for ex. vco_fun for template:
a)copy this block and paste (the location for paste is Your choice)
b) change //name field----- in my case to "FUNY_MODULE"
c) change //prefix field----- my choice was "funy"
d) change //netlist data field-----in my case "funy_module"
e) change //symbol name (note: your should creat symbol if it's needed but I have used SYM_INDQ from ADS library (I think it's not needed to explane how to creat symbol))
f) make creat_parm.... string for module parameters (using copy-paste technology) name parameters and change defaults (if you want)
That is all;
Open project, type module name in the design schematic window pop-up which is near components palletes, type enter and place new created component.

I have implemented this steps for funy_module (for ex)
and upload new ex project
(C++knowledge is not needed COPY-PASTE only)

I'm glad to help....
Thanks

Regards

tutorial in verilog a in ads

First of All, Believe me, I gave you point before reading anythings, I gave you the rest 75 points +extra 37+helped me button, I'm ready to give you any more points you need (for free, just try to ask me!)

In fact, i thought that no one will help me in this issue after the very long waiting!! but you finally did, I'm very heppy!

But I'm sorry, after i read your reply i found that there're some points i couldn't usderstand, if you can clarify them, this will be further kind of you..

Please follow me with your steps.. and be patient a bit..

1.Write verilogA module. I have implement "funy_module" in "vco_fun.va file"

Click to expand...

Done

2.Open "vco_fun.ael" file using text editor (wordpad is good choice)

Click to expand...

Where to open if from? Do you mean to open a blanck text file and name it "vco_fun.ael" or what ? clarify this point again please..

3.Use "creat_item......" block from for ex. vco_fun for template:[\quote]
I'm sorry but what's "creat_item....." block? where to get it?

a)copy this block and paste (the location for paste is Your choice)
b) change //name field----- in my case to "FUNY_MODULE"
c) change //prefix field----- my choice was "funy"
d) change //netlist data field-----in my case "funy_module"
e) change //symbol name

Click to expand...

I think these steps will be easy if i could find the ael file..

(note: your should creat symbol if it's needed but I have used SYM_INDQ from @DS library (I think it's not needed to explane how to creat symbol))

Click to expand...

I am sorry again, but i don't know really how to creat a symbol, explain how to creat it.. this is a point, another point, I don't know how could you find and use symbol of certain componant? where could you get it from?

f) make creat_parm.... string for module parameters (using copy-paste technology) name parameters and change defaults (if you want)

Click to expand...

Where to make "creat_param..." from?

I'm really unable to thank you,
Ahmad,

Click to expand...

ael tutorial ads verilog-a

Dear Ahmand
I will send WORD DOCUMENT....
But give me some time to prepare it...
Now 25.04.06, I think 26.04 You will have post

Thanks for interesting topic.

add in verilog

Grig said:

Dear Ahmad
I will send WORD DOCUMENT....
But give me some time to prepare it...
Now 25.04.06, I think 26.04 You will have post

Thanks for interesting topic.

Click to expand...

You worth thank in fact,
I'm waiting for it,

Ahmad,

add points to reward 1

Grig said:

Dear Ahmand
I will send WORD DOCUMENT....
But give me some time to prepare it...
Now 25.04.06, I think 26.04 You will have post

Thanks for interesting topic.

Click to expand...

Hi, can I also have a copy of the word document you sent? i am also having trouble finding out how to create a block directly from a verilog-A code.

verilog-a ads

Grig said:

Dear Ahmand
I will send WORD DOCUMENT....
But give me some time to prepare it...
Now 25.04.06, I think 26.04 You will have post

Thanks for interesting topic.

Click to expand...

Can I have one copy of the word document either? Thanks a lot!

Re: [150 points reward] How to add analog Verilog-A block in

Could you pl. upload the word document? I like to get a copy as well. I am stuck at the point of creating the ael file from va file. Many thanks.

How to simulate Verilog-A in ADS

ahmad_abdulghany said:

Hi,

I want to know steps to add an analog block described in Verilog-A to 'A'DS..

I am assumed to have the verilog-A model written in a text file, and have verilog-A design kit installed,

I will give 100 points as a reward for that,
Thanks alot in advance,
Ahmad,

Click to expand...

I see that years after this post originally was made, the subject is still revisited. I ran into similar problem, but i don't expect that folks that discussed these issues in 2006 would still have that file or plan to send it. So, I set down and figured out how to work with verilog-a in ADS but the process is not straight forward for novice users, so I have prepared my own set of instructions (step-by-step) with screenshots. There are still a few things to figure out that i mention in the document, but i got to a point where i successfully simulated the model that i have created. On an example of a simple DCO (digitally controlled oscillator) i show how to set up the environment and which files to edit (and how to edit).

If there are experts here who know better how to avoid some of the steps that i have shown, please do so, as it would be helpful for me as well.

I am attaching my document.

Re: How to simulate Verilog-A in ADS

This is the most detailed answer, thank you so much!
Regards!

kert said:

I see that years after this post originally was made, the subject is still revisited. I ran into similar problem, but i don't expect that folks that discussed these issues in 2006 would still have that file or plan to send it. So, I set down and figured out how to work with verilog-a in ADS but the process is not straight forward for novice users, so I have prepared my own set of instructions (step-by-step) with screenshots. There are still a few things to figure out that i mention in the document, but i got to a point where i successfully simulated the model that i have created. On an example of a simple DCO (digitally controlled oscillator) i show how to set up the environment and which files to edit (and how to edit).

If there are experts here who know better how to avoid some of the steps that i have shown, please do so, as it would be helpful for me as well.

I am attaching my document.

Click to expand...

Re: How to simulate Verilog-A in ADS

Hi there,
I found your document on VerilogA + ADS quite helpful for beginner like me.
I followed the same steps explained by you, but got stuck in middle. After modifying the ael file in step 11, when I create the new design DCO_test.dsn and add the DCO model, it has instance name x1 (and parameters b0,b1,b2,b3 were not there). I can see in your schematic it is not an issue.... When I add the sources and terminations, and simulate, ADS says incorrect number of terminals... My questions in brief are
a) do we have to include parameter called 'signout' in the modified ael file?
b) Why in my case I can't see the four parameters b0----b3 in the input section?
c) how I can solve the simulation error?

I will greatly appreciate if you can give a reply... Awaiting for your response
Prem

kert said:

I see that years after this post originally was made, the subject is still revisited. I ran into similar problem, but i don't expect that folks that discussed these issues in 2006 would still have that file or plan to send it. So, I set down and figured out how to work with verilog-a in ADS but the process is not straight forward for novice users, so I have prepared my own set of instructions (step-by-step) with screenshots. There are still a few things to figure out that i mention in the document, but i got to a point where i successfully simulated the model that i have created. On an example of a simple DCO (digitally controlled oscillator) i show how to set up the environment and which files to edit (and how to edit).

If there are experts here who know better how to avoid some of the steps that i have shown, please do so, as it would be helpful for me as well.

I am attaching my document.

Click to expand...

Re: How to simulate Verilog-A in ADS

Same here, stuck at the same step

@kert could you please explain whats wrong

bpremlal said:

Hi there,
I found your document on VerilogA + ADS quite helpful for beginner like me.
I followed the same steps explained by you, but got stuck in middle. After modifying the ael file in step 11, when I create the new design DCO_test.dsn and add the DCO model, it has instance name x1 (and parameters b0,b1,b2,b3 were not there). I can see in your schematic it is not an issue.... When I add the sources and terminations, and simulate, ADS says incorrect number of terminals... My questions in brief are
a) do we have to include parameter called 'signout' in the modified ael file?
b) Why in my case I can't see the four parameters b0----b3 in the input section?
c) how I can solve the simulation error?

I will greatly appreciate if you can give a reply... Awaiting for your response
Prem

Click to expand...

Re: [150 points reward] How to add analog Verilog-A block in ADS

Hello,

@kert:
Thank you so mucchh, now it works.

@bpremlal & @santhoshonkar:
Maybe simply after editing the .ael file try to restart ADS. I was in the same situation than you until I restarted.

Does anyone know a kind of automatic tool to preformat the ael file directly from the veriloga source file ?

Re: How to simulate Verilog-A in ADS

hi..
I read your pdf .it was really useful but I have one problem...
how can I compile "name.va",and where can I run that before adding in ADS?
can you introduce a compiler for verilog-A?
thanks alot...