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VHDL command for: if (signal changes) then do something

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tooh83

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hi
i need to know if there is a command in vhdl which can do the following :
if (signal changes) then
do sth..
and if the answer is no then how can i do it ?
thnx in advance
 

signal event vhdl

you can use 'event like :

if (signal'event)
......

This will execute what u want whenever ur signal changes.
 

what is event on a signal in vhdl

process (clk, reset)
begin
if reset = '0' then
prev_sig <= '0';
elsif (clk = '1' and clk'event) then
prev_sig <= current_sig;
end if;
process (clk)
if (clk = '1' and clk'event) then
if prev_sig /= current_sig then
<<< DO SOMETHING>>>
end if;
end if;
end process;
 

    T

    tooh83

    Points: 2
    Helpful Answer Positive Rating
vhdl if signal changes

Process(signal)
begin
do something;
end process;
 

    T

    tooh83

    Points: 2
    Helpful Answer Positive Rating
Re: vhdl question

Foo: Process
Begin
Wait until signal'event;
...
End Process Foo;
 

Re: vhdl question

for a signal....u can use the "event" attribute to test if its value changes or not

signal'event
 

Re: vhdl question

yes u can, go through this code . If any problem fee free to contact

library ieee;
use ieee.std_logic_1164.all;

entity flipflopT is
port( clk,t:in std_logic;
q,qq: out std_logic);
end flipflopT;

architecture arch of flipflopT is
signal tmp: std_logic;

begin
process(clk)
begin
if clk'event and (clk='1') and t='1' then tmp <=not tmp;
end if;
end process;
q<=tmp;
qq<=not tmp;
end arch;
 

Re: vhdl question

Why not use this?

process(signal)
begin
do st
end process;
 

    T

    tooh83

    Points: 2
    Helpful Answer Positive Rating
Re: vhdl question

process is one construct tht can be used to solve ur problem.
The other way is u can use event for that which will be as follows.

ex: if the signal on which ur waiting is say "ret' then code looks as below

process(ret)
begin
////do something

end process

this results in a combinational logic
if event is used then that would also result in a sequential logic....
 

    T

    tooh83

    Points: 2
    Helpful Answer Positive Rating
Re: vhdl question

process(signal)
begin
do st
end process;
 

Re: vhdl question

tooh83 said:
hi
i need to know if there is a command in vhdl which can do the following :
if (signal changes) then
do sth..
and if the answer is no then how can i do it ?
thnx in advance
Click to expand...

Of course !
u can try like this sequential statement :
IF (clk = '1' and clk'event ) THEN
zout <= '1';
ELSE
zout <= '0';
END IF;

but this code just be right if it is written in the PROCCESS statements .

let try !
 

Re: vhdl question

hi

there are 3 ways

1. a wait statement at the end or the beginning of the process

eg. wait on a

if 'a' changes then the process with re-evaluate

2. a sensitivity list in the process

eg. process (sensitivity list) --process (a)

3. and if statement with an event

good luck
 

vhdl question

I prefer using rising_edge(sig) and falling_edge(sig) functions :)
 

Re: vhdl question

i have signal name "NUM"(8 bit),
i want to start a state machine while NUM is changed,and this state machin is under a process(clk),
i have tried these
1> i wrote
if NUM'event then
---state machine start
=================
here the error is
line 97: unsupported Clock statement

2> i wrote
wait on NUM;
============
the error is
statement WAIT not allowed in a process with a sensitivity list

3>i include the NUM to process sensitivity list also

the error is
=============
Signal "name of the current state of my state machine" cannot be synthesized, bad synchronous description.
 

Re: vhdl question

You should try to get a more thorough understanding of the VHDL event concept. You can either have a synchronous (clock edge sensitive) or a combinational (state sensitive) process. In addition, an asynchronous condition can be combined with a clocked process, e.g. as a reset.

But you can't have additional events inside a clocked process. I notice, that your chasing the idea of additional events in a process since long. Apparently you didn't yet get through to the basic VHDL concepts behind.

In my view, there's no room for additional events in a clocked process, e.g. a state machine. If you want to detect a change in a particular input condition, you can compare the present signal state with the registered previous state and act according to the compare result.
 

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