LC VCO tuning to get the ideal w

hi


How can the C-V characteristics of a varactor, that is being used in a LC VCO, be influenced, so that the ideal w=1/sqrt(LC(V) can be obtained??


And also, how can the output frequency be adjusted to approach the ideal tuning characteristic?

I know the varactor capacitance is influenced by the oscillator output voltage swing, and to some degree the LC-tank losses.

The performance parameters phase noise and low power consumption are not of primary importance, can the ideal characteristic be obtained at the expence of these??

cross coupled pair

Varactor diode connection introduces parasitic which degrades the Q factor, hence the ideal characteristic of the tunable capacitor. IN order to enhance the Q use larger value of varactor capacitor for higher frequency application in pMOS VCO topology. This would compensate the mismatch and reduce losses.

Rgds

tuning curve vco

Thanks for the reply.

I am using a MOS transistor in inversion-mode as varactor, due to its scalabillity with lower supply voltages, and I know Q-factor may be higher for the MOS varactor, than for the reverse biased diode varactor.

If i increase the length of the MOS transistor, the capacitance range will increase due to increase in the transistor areal, and also the resonanse frequency will be shiftet to a higher frequency.
However, the increase in the MOS transistor length will degrade the LC-tank Q-factor, due to increased of resistance in the transistor channel.

Also, i don't think the Q-factor is the main problem for the ideal w=1/sqrt(Lc(v)) characteristic, but rather the large amplitude swing at the oscillator output, that influence the effective capacitance of the varactor.

This tank amplitude can be controlled by the bias current, when in the current limited region.
I have tried to reduce the tank amplitude to approach the w=1/sqrt(L(C)), and to some extent the tuning curve of the oscillator was corrected..... but still, there is need for improvement, so im wondering what other steps that should be taken?

For instance, how should the MOS transistor lenghth and width be set? (I know this depends on what what resonsanse frequency, and tuning range i want, but to obtain the ideal characteristic is the primary objective.).


Still hoping someone can give me some ideas

Saber890

lc vco swing

Hi Saber90
Sizing of the cross coupled MOS transistors, as you may already know, has to be such that gm * Rp = 2 for sustained oscillations where Rp is the parallel resistance of the tank ckt. Once the gm value is arrived at and the current is known, use the minimum W/L to achieve the required gm, so as to add minimum cap to the tank. Hope this helps...
Rgds
Maddy

lc vco nmos w/l

thanks Maddy

Your suggestion helps reduce the paracitic capacitance contributed from active elements that provide the negative conductance (gm), so this increases the Cmax/Cmin ratio, leading to a increase in the available tuning range for the VCO.

In order to keep the parasitic contribution low, I am using a single cross VCO topology, and not a double cross-coupled one.
But I dont know which of the single cross and the doubley crossed, would be the best fitted in order to get the best (most accurate), C-V curve, and from there the best w=1/sqrt(L*C(V)) tuning curve.


Further I would like to know how the large signal at the VCO output affects the increased capacitance range. I know a increase in the output amplitude will make the transaction from Cmin to Cmax( or vise versa), "smoother". In other words, the steepness of the C-V characteristics is smoothed out in the frequency tuning curve, as the Cmax-Cmin transaction takes longer time with a higher oscillating amplitude.

If there are any other suggestion, please let me know

Saber890

vco current limited voltage limited

Hi Saber890
With a Complementary cross coupled pair, same current generates a gmn (NMOS) and a gmp (PMOS) and hence the devices can be smaller meaning lesser parasitics. If it were a PMOS only pair which is used for better Phase Noise (low flicker) then the devices are going to be larger because of low mobility. A NMOS only might be better in terms of sizing but Phase Noise will suffer. I am not sure how stringent your Phase Noise at low offset ~ 100 KHz is.

My guess is the one with least parasitics will be closest to the C-V curve.

Not sure on the VCO ampl and capacitance range.

Rgds
Madhav

vco current tuning

I study M. H. Perrott lecture notes

**broken link removed**

according to the notes
the design procedure of LC VCO
1) design tank components to achieve high Q
2) choose bias current for large swing without going far into Gm saturation.
3) choose W/L to achieve adequately large gm

I do not understand what is the meaning of the large swing without going far into Gm saturation?
Please let me know...
Thx in advance.

lc vco voltage swing

There are two regions of operation for the VCO, first there is the Current limited region, where the bias current (or the inductor) can be used as an independant variable in order to increase the amplitude of the oscillator output swing.

However, at a certain point the amplitude will no longer grow with the bias current, then the VCO is operating in the Voltage limited region(the supply voltage sets the limit for the voltage limited region). When the voltage limited region is reached, increasing the bias current doesn't increase the output amplitude, it leads to waste of power.
Increasing the output amplitude swing has a positive effect on the phase noise.
Often the best trade-off between phase noise and power consumption is at the border of the current-and voltage limited regions.

mh perrott lectures

When I try to simulate the LC VCO with 1.3GHz,
I observed that it can not be oscillate if I use
fab. provided inductor and varactr model.
I heard that it is due to the gm of the NMOS is not high enough at
high freq after including all parasitic component.
Is it possible for me to simulate the gm freq response of the NMOS in LC VCO?