Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Looking for fifo build by fpga

Status
Not open for further replies.
S

somayeh

Newbie level 5
Newbie level 5
Joined
Apr 15, 2006
Messages
8
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,343
building fifo by fpga

Hi people,

Could anybody go forward and build something?
Any interesting to share ??

Regards,
 

Re: building fifo by fpga

what is the problem ?

you can use xilinx coregen to generate fifo.

if you want to generate your own fifo, just use a DPRAM, with your own address counters, and control signals.[/i]
 

Re: building fifo by fpga

these documents might be useful if you are planning to design a fifo yourself

hxxp://www.geocities.com/deepakgeorge2000/vlsi_book/Asynch1.pdf
hxxp://www.geocities.com/deepakgeorge2000/vlsi_book/async_fifo2.pdf
 

    S

    somayeh

    Points: 2
    Helpful Answer Positive Rating
Re: building fifo by fpga

You can easily build it. Try


Generate a set of registers and shift/rotate the data side by side for each clock cycle.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top