How do I connect dummy layout element ?

for layout matching, some book recommend that circuit designer have to use dummy element.

okay. I understand why dummy elemnt are needed. But I don't know where do I connect to dummy element.

I have to them in floating state? or connect some other node?

All dummy element have to connect to only one node?

If I have to connect to some node, Why do I have to do?

thanks

Try shorting all terminals to gnd. It is just for layout but to clear LVS, you have to put a component in Schematic too.
Maddy

Not at all the time.

If its an NMOS dummy, connect all nodes to the vss and if its the PMOS dummy,
connect it to the vdd and i hope you know where the dummies in resistor has to
be connected.

I don't know if the metal structure matters, but it might be something to think about (make dummy metal symmetric with the real devices). Can anybody comment on this?

What sooraj told is absolutely correct.
But, As you know every micron of silicon costs something, So, I will recommend you not to waste the transistors by making it dummy. Instead you can use those dummies as moscaps.
Ex: Connects source and drain of NMOS dummy to VSS and Gate of this NMOS to VDD. This doesn't applies always due to routing constraints.

Added after 32 seconds:

What sooraj told is absolutely correct.
But, As you know every micron of silicon costs something, So, I will recommend you not to waste the transistors by making it dummy. Instead you can use those dummies as moscaps.
Ex: Connect source and drain of NMOS dummy to VSS and Gate of this NMOS to VDD. This doesn't applies always due to routing constraints.

In today's advanced nodes of 130 and below, it is no longer feasible or recommended to make MOS Caps with un-used transistors. Making dummies are fine. In advanced nodes, leakage is a very serious issue, thus making MOS Caps only increases power consumption due to leakage!
Forget about making MOS Caps. In fact, in static CMOS circuits, due to the parastic caps in the MOS transistors, transistors that are not switching are in fact symbiotic caps. I presume you know this too.

when u have to do matching with odd no of transistors no way other than dummy .

definetely it should be connected to some potential it cannot be floating.

The dummies have to be connected to Vdd or Vss

However, for ESD issues you cannot directly connect them to Vdd or Vss. Rather, a soff pull circuit is used to avoid having gates directly connected to an IO pin ( may cause serious damage ).

dummies not only provide electrical isolation but also provide the similar processing environment,as to the later situation,I think we can just hang them up

Dear All,

can one of you explain to me the utility of dummies is it to clean DRC of density errors ?? or have onoher goal..
is there some sites in the net talking about it (i have issue in SEALRING)
is there some links

Help

THX g@fsos

I am not sure that I completely agree with SkyHigh about not using MOS as capacitors. The primary leakage in small geometry devices is source-drain leakage. What this leakage essentially means is that the device can not be completely turned off. In the case of a MOS cap, the source is tied to the drain, so THAT leakage is unimportant.

As gate oxides get thinner, there is some increase in gate leakage, but that remains a very small term.

Leakage from the source or drain to the substrate or well can also be an issue, but typical MOS caps will have zero bias from source/drain to well or substrate.

The MOS cap is not good for many analog uses since it will have a large change in capacitance with voltage, but as a filter cap on the gate of a current source, for example, the MOS cap is just fine, and using the dummys for this purpose should not cause a problem, in my opinion, particularly if one end of the cap is connected to the power supply.