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Generating a 90 degree phase shift clock

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colette

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Hi

I have two clocks in the system, 128mhz and 64mhz, I want to generate a 90 degree phase shifted 64 mhz clock. The fpga does not have a pll or dll, any advice would be greatly appreciated
 

colette said:
Hi

I have two clocks in the system, 128mhz and 64mhz, I want to generate a 90 degree phase shifted 64 mhz clock. The fpga does not have a pll or dll, any advice would be greatly appreciated
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This is quite simple if you have a 2X clock (ie, you have 128 MHz already).
Pass the 128 MHz through a clock divider - back-to-back flip flops configured in feedback - refer to any standard book on flip-flop based dividers.
The intermediate node in the divider will have a quadrature (90 deg phase shifted) version of the 64 MHz clock and the other node will have the 0 degree reference for the 64 MHz clock.
 
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    colette

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    Steva

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Hi

Am I correct in assuming that both fflops are clocked from 128mhz, the connection to the D input to the first fflop is the complementary o/p of the second fflop and the Q o/p of the first fflop is connected to the D input of the second fflop.

Thanks for you help
 

entity clkgen is
port (
128mhz : in std_logic;
64mhz : out std_logic;
shifted_64mhz: out std_logic);
end entity;

architecture arch of clkgen is
signal int1, int2 : std_logic_vector (1 downto 0);
begin
process(128mhz) is
begin
if (128mhz=1 and 128mhz 'event) then
int1 <= int1+1;
end if;

64mhz <= int1(1);

end process;

process(128mhz) is
begin
if (128mhz=0 and 128mhz 'event) then
int2 <= int2+1;
end if;

shifted_64mhz <= int2(1);

end process;

end architecture;
 

Here I have corrected the code!
Code: 
entity clkgen is
  port (
    reset         : in  std_logic;
    128mhz        : in  std_logic;
    64mhz         : out std_logic;
    shifted_64mhz : out std_logic);
end entity;

architecture arch of clkgen is
  signal int1, int2 : std_logic;
begin
  process(128mhz, reset) is
  begin
    if (reset = 1) then
      int1 <= '0';
    elsif (128mhz = 1 and 128mhz 'event) then
      int1 <= not int1;
    end if;
    64mhz <= int1;
  end process;

  process(128mhz, reset) is
  begin
    if (reset = 1) then
      int2 <= '0';
    elsif (128mhz = 0 and 128mhz 'event) then
      int2 <= not int2;
    end if;
    shifted_64mhz <= int2;
  end process;
end architecture;
 

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