Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
i think the reason maybe the delay of the inverter is smaller than a buffer,
so, the clock skew maybe smaller(of course you can insert buffer in other path to balance the clock skew, but i will cause extral area and power consumption)
as tarkyss said inverter delay is lesser than buffer for the same drive capacity. buffer is basically 2 inverters connected back to back. so the insertion delay [modelled by set_clk_latency in DC]of the clock tree will be lesser.
Clock buffers and clock inverters are usually built to maintain uniform duty cycle. The main difference is in the area where buffer uses a higher area to drive a signal to certain distance before it has to be rebuffered. If inverters are used , you can drive the signal to the same distance with almost half the number of cells.
Clock buffers and clock inverters are usually built to maintain uniform duty cycle. The main difference is in the area where buffer uses a higher area to drive a signal to certain distance before it has to be rebuffered. If inverters are used , you can drive the signal to the same distance with almost half the number of cells.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
