Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

how to use write_sdf command ?

Status
Not open for further replies.
Q

quan228228

Full Member level 4
Full Member level 4
Joined
Mar 23, 2006
Messages
196
Helped
16
Reputation
32
Reaction score
3
Trophy points
1,298
Activity points
2,571
write_sdf

hi,
When i sythesis a design and then do a simulation. I found some warning in log when simulating.
Whe warning is like below:

Warning: Timing violation:.................

There are thounds of the warning. Why ? Did i use the comand "write_sdf" wrong in synthesis scripts?
In the scripts"
write_sdf -force_caculation -edges noedge -interconn none -nonegchecks -version2.1 /netlists/ cm3206.vg"

Help me?

Regards
/David
 

sdf generic write_sdf

i think many reasons: 1. you constrain mismatch your simulation invironment . 2. two clock domain

Added after 1 seconds:

i think many reasons: 1. you constrain mismatch your simulation invironment . 2. two clock domain
 

    Q

    quan228228

    Points: 2
    Helpful Answer Positive Rating
write sdf triplet

check whether RST/PRESET etc are asserted /deasserted with proper timing. suggest to assert them on the unused edge of the clock
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top