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Question about signal integrity

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EDA_hg81

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limitation in signal integrity

I understand the trace proper termination method depends on raising and falling time of I/O port and geometry of trace, etc.

My question is as following,
Does the main clock frequency (such as 200MHZ) has any relation with raising and falling time of I/O port?
If main clock has nothing with I/O port, if the same trace termination method is going to be used for the same I/O port under 60MHZ or 500MHZ?

Thank you for your any ideas.
 

The rise and fall time is determined by the logic family being used, and some would also add in the capacitance of the associated traces, usually termination for logic is meant to match the ideal impedance for the logic being used, and sometimes, as in the case of thevenin equivalents it can also set a default logic state for an inactive line, in short, the frequency would have no bearing on resistive termination schemes, I'm not so sure about capacitive termination, but judging by what I've seen frequency shouldn't be an issue either.

SiGiNT
 

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    EDA_hg81

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Is my understanding as following right?
The upper limit of running clock frequency of FPGA chip is depended on the raising and falling time of I/O port.
Thank you.
 

the rise and fall times depend only on the load capacitances. if u use a RC pair for teminating ur I/O lines, then the terminators would behave in an unexpected way if u change the bus freq. a series tremination has to work while u change the freq. even parallel or thevenin terminations may introduce unwanted effects due to improper pull up and pull down + ESL that may reflect on the rise/ fall times.
 

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    EDA_hg81

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to be more general, rise and fall times depend on the
logic family. BUT, usually they are connectd trough a
CHANNEL(serial line,microstrip, fiber,etc) which ALWAYs
has a limited bandwidth. Because this limited bandwidth
the channel could modify the rise/fall times. The band
width should be higher than the knee frequency of
clock signal plus other limitations as jitter, ringing,
settling time, etc
That impose a limitation on the speed of the clock.
 

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    EDA_hg81

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jallem said:
to be more general, rise and fall times depend on the
logic family. BUT, usually they are connectd trough a
CHANNEL(serial line,microstrip, fiber,etc) which ALWAYs
has a limited bandwidth. Because this limited bandwidth
the channel could modify the rise/fall times. The band
width should be higher than the knee frequency of
clock signal plus other limitations as jitter, ringing,
settling time, etc
That impose a limitation on the speed of the clock.
Click to expand...

...yes rise time and fall times are decided by the band limiting factors of ur logic gates, probes, wires, transmission lines...simply all through the way the current flows its rise/ fall time is degraded
but i think only the RC termination will have more effect wrt the freq...
 

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    EDA_hg81

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