saber890
Newbie level 6
![Newbie level 6](/styles/images/ranks/blevel3.gif)
mos varactor simulation cadence
How can i extract the gate- capacitance variation of the MOS transistor, in the Cadence analog design enviroment, dc signal analysis?? Im using the varactor in a LC VCO design, and want to get a good as possible estimation of the ideal LC tuning characteristics.
-Saber
How can i extract the gate- capacitance variation of the MOS transistor, in the Cadence analog design enviroment, dc signal analysis?? Im using the varactor in a LC VCO design, and want to get a good as possible estimation of the ideal LC tuning characteristics.
-Saber