davyzhu
Advanced Member level 1
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Hi all,
I heard that Verilog has integer type.
Someone said integer can be signed or unsigned.
How to declare signed integer?
And what's the difference with integer and reg signed [31:0](2's complement) ?
Any suggestions will be appreciated!
Best regards,
Davy
I heard that Verilog has integer type.
Someone said integer can be signed or unsigned.
How to declare signed integer?
And what's the difference with integer and reg signed [31:0](2's complement) ?
Any suggestions will be appreciated!
Best regards,
Davy