Why we get metal density violation?

metal density violation

hi ...

why we get metal density violation?

thanks

metal density violation

this is a pre-layout and drc problem. you must solve your question of layout at first.

metal density violation

Both etching and planarization processes used in manufacturing require an even density of metal to be left across the chip
it is a requirement for DFM(design for manufacture) or DFY(design for yield)

Re: metal density violation

Background:
The thickness of dielectric layers vary due to the different patterns of metal on successive metal layers. These variations will impact yield.

Insert metal fill to increase metal layers's metal density, and make the topology of all the metal layers more uniform, therefore reduce the thickness variations.
-------------------------------------------------------------------------------------

Reason:
Depends on the design, metal pattern may not distribute enough in some region duing routing phase. Therefore, metal dendity violations occur.
--------------------------------------------------------------------------------------

Impact:
Insert metal fill may affect both timing & sinal integrity.
---------------------------------------------------------------------------------------

metal density violation

You can fix it in P&R tools.