How does the attached low power buffer circuit work?

how it works

Hello

I have a problem with this circuit.

it should work as a low power buffer. i've got a DC characteristic form an article and it's linear with the slope equal to 1.

i cannot achieve slope=1 the top part has almost 1V/V(when works alone) but the bottom has about 0.7V/V

can it be related to low vdd=1.3V ?

Voltages at A and B follow Vi and turn on/offtransitors M3P and M3N

There is also a voltage shift between vi and A or B eguals to Vgs so how the buffer can translate Vin to Vout?

anyone did that?

regards

Re: how it works

If you use n-well process, NMOS bulk is connected to the ground , which makes that NMOS is not ideal source follower. As a direct result of bulk effect source follower has gain smaller than 1.
In the case of PMOS you can connect bulk to source and you dont have problem with bulk effect, which means that gain can be 1.
If you need detailed explanation just look into Razavi´s book...

Re: how it works

pixel said:

If you use n-well process, NMOS bulk is connected to the ground , which makes that NMOS is not ideal source follower. As a direct result of bulk effect source follower has gain smaller than 1.
In the case of PMOS you can connect bulk to source and you dont have problem with bulk effect, which means that gain can be 1.

Click to expand...

thanks for reply

right, but i can't use both n-well and p-well processes. i don't know how they did it in this article so achieved overall gain almost 1V/V

is there any way to improve that? i need a buffer for 1.3 vdd which will work with 0.3 and 0.6V I would use pmos source follower or ota with pmos inputs but |Vthp| is about 0.75V and i simply have no voltage to work properly.

complementary buffer would be ideal

regards

Re: how it works

NMOS bulk is connected to analog ground, and you will always have bulk effect problem with nmos whoose source is at the different potentional than gnd (M1n).
Maybe you could add bulk effect to pmos (M1p). Connect PMOS bulk to VDD instead of source. Then you will also have source follower with smller gain than unity, but symetrical.

Re: how it works

hi
This is how i see it....each block(TOP and BOTTOM) can be seen as a diff-single ended differential amplifier with the output connected to the inverting input and constant current source fed with common-mode f/b. Combined blocks operate over the supply-range.
This structure has the following drawbacks:
1) The NMOS and PMOS pairs at the input operate in opposite regions, i.e BOTTOM block as strong for high inputs. but NMOS is not good for pulling output nodes high and similarly the PMOS block is not good for pulling the node low.

Remedy: Try to reverse the input pair and make appropriate changes.

2) The drain node of the input pairs are directly connected to the gate of current-source. This causes a reduction in common-mode range. This is possibly why your are getting 0.7V/V.

Remedy: Use a level shifter between the drain and the gate of current-source.

3) The output node is low impedance node due to diode connection. This may push the output pole closer to non-dominant pole thus reducing your GBW.

Remedy: Look at other alternatives like push-pull output.

regards

Re: how it works

I don't think you guys catch the essence of this wonderful design: it is a bootstrap cicuit and can overcome the source follower limitation of NMOS device. Thus, with proper design, the gain can be very close to unity.

Re: how it works

First look at translinear principle (in Bipolars). This is also a translinear circuit in CMOS. Vin=Vo if not something wrong in your circuit like you connected or better not connected wells of transistors properly.

Your slew rate is by the difference of sinking/sourcing current capability. Check the ro of ( -> sizes of) M2P and M2N. these two transistors are need to be equal strength. you will see it when you play around with their sizes.

Good luck.

Re: how it works

willyboy19 said:

I don't think you guys catch the essence of this wonderful design: it is a bootstrap cicuit and can overcome the source follower limitation of NMOS device. Thus, with proper design, the gain can be very close to unity.

Click to expand...

you mean, it should work properly even with vdd=1.3V and |Vthp|=0.75 Vthn=0.55?

for vdd=3.3 it works ok, but, has a input swing from about 0.8 to 2.2V

Re: how it works

tekno1 said:

Your slew rate is by the difference of sinking/sourcing current capability. Check the ro of ( -> sizes of) M2P and M2N. these two transistors are need to be equal strength. you will see it when you play around with their sizes.

Click to expand...

is here discussing why the gain can't reach 1 when vdd is low not the slew rate?

Added after 8 minutes:

willyboy19 said:

I don't think you guys catch the essence of this wonderful design: it is a bootstrap cicuit and can overcome the source follower limitation of NMOS device. Thus, with proper design, the gain can be very close to unity.

Click to expand...

how to explain it?