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what will happen if we dont use filler cells?

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coolrak

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Hi Everybody,.

I understand that we need filler cells to fill the gaps in standard cells.But I want to

know what will happen if there are gaps in standard cells.

Thanks in advance
 

It doesn't matter if there is gap, but it's a waste to leave the space open. The filler cells can be used as ECO spare cells. When chip is back with some bugs, you can use these cells to do metal ECO.
In case you do any ECO, you can try the GUI netlist ECO tool, GOF, which can do functional/metal ECO. Check the link out
https://www.nandigits.com/metal_only_eco.htm
 
Hi Nandy thanks for the information. But inserting filler cells is negatively affecting my

timing. I want to know the negative affects if we dont put filler cells.

Thanks in advance
 

You are not supposed to move the normal cells when inserting the filler cells.
Only when timing is clean, you can do the insertion.
You would have difficult to do metal ECO if there is no spare cells (filler cells)
 

I think inserting fill cells is for mechanical concern.
 

I also think inserting filler cells is for metal ECO, as description of Nandy, but greensand's hears with reason, too.
 

The filler cell is used to connect well and power line of standard cell and to do this is good for yield.
 

hi jcchan,
jcchan said:
The filler cell is used to connect well and power line of standard cell and to do this is good for yield.
Click to expand...

could u plz explain this?
i m not sure how this effects the yeid?
 

Hi Guys,

Filler cells is not related to yield, mechancial stress etc. It is also not to connect power rail.

The main reason for filler celll is not to have DRC. For example, every standard cell has a nwell. If two standard cells are place side by side with a gap (the smallest gap is called the placment grid. It is larger than the manufacturing grid. Maybe it is M2 pitch, I am not sure...), then there will be a nwell-to-nwell DRC violation. By closing the gap with the filler cell, than it the nwell in the filler cell will abut the nwells into one nwell.

Since we need filler cell, additional function has been added to the filler cell, like well/substrate tap, transistor array, decoupling caps etc.



Regards,
Eng Han
www.eda-utilities.com
 
Hello leenghan, your's speaking is very clear, but could you sure that the filler cell is only for DRC check?
 

hi leeenghan,
Thanks for the information.You explanation is very good.
 

Hi semi_jl,

The main reason is not to have DRC, but it is not the only use. To summaries, if you don't put filler cell, than you will have DRC error.



Regards,
Eng Han
www.eda-utilities.com
 

There is a CMP process in chip fabrication process,

it require some amount of metal density to ensure

CMP's uniformity, so we need filler cells to fill

the gaps.

best regards




coolrak said:
Hi Everybody,.

I understand that we need filler cells to fill the gaps in standard cells.But I want to

know what will happen if there are gaps in standard cells.

Thanks in advance
Click to expand...
 

Can we assume that if std.cells are placed in different rows, its possible to use filler cell as feedthrough to connect them using vertical routing ?
 
Hi r_p_sanna,

You can do this, but you shouldn't. Use placement blockage to do this.

If there is no metal geometries in the filler except at the power rail, then filler cells should be inserted after detailed routing or just before tape-out for full DRC/LVS check. If not, it can be insert after CTS (just before detailed routing).

Regards,
Eng Han
 

Hi, leeenghan, I think I should agree with you.
 

Hi,
thanks for the info. Read about feedthroughs in ASIC book, but wasn't sure about using it in filler cells.
 

Hi,

Thanks Leenghan and Funster for ur valuable inputs.
Does anybody have some reference to get more idea and how it can be done??

Thanks
 

what are the DRC violations we are getting placing nwells of two standard cells side by side?
 

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