EDA_hg81
Advanced Member level 2
vga timing
Please help me to find out the VGA timing description.
Can I realize two FPGA share one SDRAM by sharing the data bus and control bus of SDRAM?
Thank you
Please help me to find out the VGA timing description.
Can I realize two FPGA share one SDRAM by sharing the data bus and control bus of SDRAM?
Thank you