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need help for VGA timing description

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EDA_hg81

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vga timing

Please help me to find out the VGA timing description.
Can I realize two FPGA share one SDRAM by sharing the data bus and control bus of SDRAM?

Thank you
:cry:
 

gtf_v1r1.xls

You can try to impliment SDRAM controller in one FPGA and make interface to another one, or even something different let's say two fpga connected to one CPLD with SDRAM controller on it.
Sharing one SDRAm between two FPGAS your layout will complicated, and also you will need to have two SDRAM controllers which is resource waste, and somehow to sync those controllers

Good Lack!
 

    EDA_hg81

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vesa vga data timing

Thank you all.

this really helped me.:|
 

hwang-172.pdf

Hi, Gentlemen!
Does anybody remember VESA?
Study this document **broken link removed**
It will help you to calculate timing parameters for any resolution.

GTF means "Generalized Timing formulae".

Regards, YUV.
 

    EDA_hg81

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vga timing parameters

YUV,


Do you have user name and password for the VESa site.


Thanks,
 

gtf vga timing

Iouri said:
YUV,
Do you have user name and password for the VESa site.
Thanks,
No, I don't. But the folder /public/ is opened for everybody.
 

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