pls clear my doubts on memory design

MY PROJECT IS ON THE LOW POWER DESIGN OF SRAM. FOR PROPER FUNCTIONING OF THE SRAM WE HAVE TO ADJUST THE SIZE OF THE TRANSISTORS. MY MAIN DOUBT IS

1. IS IT ENOUGH TO ADJUST THE WIDTH IN THE MODEL FILE ITSELF THAT WE R CURRENTLY USING FOR ALL OTHER TRANSISTORS.

2. OR WHETHER WE HAVE TO USE A DIFFERENT MODEL HAVING THE REQUIRED WIDTH .

3. IS THERE ANY OTHER PARAMETERS THAT HAS TO BE CHANGED ALONG WITH THE WIDTH.



MY PROJECT MAINLY CONCENTRATES ON THE LEAKAGE REDUCTION IN SRAM.PLEASE CLEAR MY CONFUSIONS.THANKS IN ADVANCE.

hi,

first of all if u want to change model file that contains model parameter that are being extracted from them fab process, than the simulation will be affected.

but u can vary the size of transistor if u want to change.

hope that this will help

Hi..
Your query is not clear.
But changing wdith in model file might not help you in case you are using some netlist and passing values through that netlist to the model file..
Please specify how you are using models ?
For leakage reduction you can also change the length of the transistor ..

I deem you should change the longth along with the width to a appropriate value, in addition, you should change all the transistors' width pro rata.
I got these information from a book, as a reference!

hmm, things are not that easy my friend, and changing the width is not the only parameter here. You say you are now focused on the leakage power, but if we also do not consider the elimination of power-related failures by addressing voltage-drop and EM, there is another effect that contributes to the total power dissipation; dynamic power. You should probably know these concepts, but just in case, dynamic power occurs when a transistor switches state and is due to capacitive charging and discharging whereas leakage power arises due to leakage current flowing through the transistor.

Since you are now focussed on the leakage effect, lets go with it. Here are the bad news leakage current can even consume power in standby or sleep modes of operation. Besides, with each step down in process geometry, leakage power has more or less doubled in magnitude, namely for 90nm process technology, leakage power contributes 40 to 50 percent of the total power budget, with active power dissipation from transistor switching making up the rest.

you are now saying that you will increase the width for the sake of decrease in leakage effects, but once the width is increased, the device thresholds also increase. You will be needing higher supply voltage requirements, and that will lead an increase in the dynamic power dissipation!

Well, actaully what i am saying it, rather than focusing on the width and stuff, look at the big picture, look at the system as a whole. there are some trade-offs to consider here.

Hi,
Here are my Answers:
1.Don't adjust the width in the model file .
c the SPICE file provided the fab generally has a no. of combinations of transistor widths that can be manufactured, they give sumthg like Wmax for a L.
n anyways not all your transistor in SRAM will have same W so, changing model file won't do u any good.
2.this question depends on which level ur using currently.
3.n yes, many parameters change when W changes.

n good luck for leakage reduction issue.