FIFO - Synthesis or Manual ?

fifo gate level

We are working on a project where we want to implement a SERDES. Of course it is mostly analog circuit design, meaning, each block is treated transistor level and analysed and layout will be manual.

There is a FIFO block though which uses two clocks, one from the reference clock from the INPUT data stream. The second is the internally generated clock from the CDR loop. Question is, from my reading, FIFO block looks like a pure DIGITAL block, so what is the methodology that you suggest in its design?

My collegues are using the analog design steps:
1) circuits
2) schematic simulation
3) layout and parasitic extraction and so on.

But i am assuming for the FIFO block it would be a digital design methodology. Can you give me a summary of the design steps. Thank you.

HDL coding->Simulation->Synthesis->Gate Sim->Physical synthesis.

Thanks. Actually the final gate level to transistor level. I can understand that from an ASIC or FPGA point of view. Coz its got standard macro cells and all. Now for me in an analog design project, we got a raw silicon, and you know, we do the floor planning, each one manually does his layout and we integrate it. For a gate level to be synthesized to a layout which can be used in that sense, what are the steps ?

gliss did captured the steps you needed to take. Based on your flow, the only one missing is to dump the physical synthesized result into GDSII format, and import back to Cadence. Though you need to be somewhat creative when it comes to do top level LVS...

well, that does not sound familiar to you, designing a full custom fifo does not take that much time either.

just divide two part

Analog part: just as you say,do circuit gate level design.

Digital part: use hdl language to implenment FIFO,then do function simulation,Synthesis.

After layout ,do postsim as possible!