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Why N-well Process but not P-well Prcoess????

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scottieman

scottieman

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Hi all,

Suddenly have a question in my mind on CMOS technology. To have both NMOS and PMOS, we need a p-substrate for NMOS and a n-substrate for PMOS on the same silicon. That is why we do have a N-well in p-sub wafer.

However, why don't we do the opposite. Use n-sub with P-well to achieve the goal of CMOS.

Anyone can tell me the reasons behind it?

Thanks alot
Scottie
 

one of the reason may be , in design we use multiple positive voltages and common ground. so entire psub is connected to gnd and n-well can be isolated and connected to multiple supplies . but if we take nsub how can we connect it to multiple supplies. then we have to use twin well process which is costly process.
so this may be one of the reason. i am glad to know the main reason .
 

Some devices are manufactured with N-sub also.
For example some LCD controllers that charge pump negative high voltage.
 

scottieman said:
Hi all,

Suddenly have a question in my mind on CMOS technology. To have both NMOS and PMOS, we need a p-substrate for NMOS and a n-substrate for PMOS on the same silicon. That is why we do have a N-well in p-sub wafer.

However, why don't we do the opposite. Use n-sub with P-well to achieve the goal of CMOS.

Anyone can tell me the reasons behind it?

Thanks alot
Scottie
Click to expand...

We try to use nmos in our design if we have option between nmos and pmos. Why? one of the reason is that, the mobilty of the carrier for nmos is higher than pmos. So, with smalll w/l of nmos we can get what pmos can give. That means small real estate for nmos in IC which mean lower cost for product. There are few more reason in term of performance in which nmos is better. In fact, before we have CMOS tech, circuitry was made up by nmos. So, I don't see any good reason to use n-sub instead of p-sub.
 

pbs681 said:
scottieman said:
Hi all,

Suddenly have a question in my mind on CMOS technology. To have both NMOS and PMOS, we need a p-substrate for NMOS and a n-substrate for PMOS on the same silicon. That is why we do have a N-well in p-sub wafer.

However, why don't we do the opposite. Use n-sub with P-well to achieve the goal of CMOS.

Anyone can tell me the reasons behind it?

Thanks alot
Scottie
Click to expand...

We try to use nmos in our design if we have option between nmos and pmos. Why? one of the reason is that, the mobilty of the carrier for nmos is higher than pmos. So, with smalll w/l of nmos we can get what pmos can give. That means small real estate for nmos in IC which mean lower cost for product. There are few more reason in term of performance in which nmos is better. In fact, before we have CMOS tech, circuitry was made up by nmos. So, I don't see any good reason to use n-sub instead of p-sub.
Click to expand...

Thanks.

Still, as I known from the web searching, alot of old technology were with n-sub rather than p-sub. That is what I want to ask, why people try to change from n-sub to nowadays p-sub. What I believe is there must be a resone or some reasons for this substrate change.

Scottie
 

I agree with pratyusha, but the multiple operation voltage is the key reason.
 

answer #1, when silicon crytal is pulled by one seed out of the furnance.
It's p- type, so it's cheapest to use p- wafer.

answer #2, Foundry implant boh Nwell and Pwell. Some need only draw Nwell, and they use reverse tone photo mask to implant Pwell.

answer #3, lots of people use n+ wafer for high speed logic, but that is more costly. And process would be slightly different.

In a hurry, bye!
 
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