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Error generated by Design_analyzer from synopsys (DDX-2)

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Aminos

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i was trying to synthesize my project using design_analyzer and analyzing step works correctly, but the elaborating steps generates this message:
"ERROR: in design 'multiplier', connectionto port 'a' of instance 'half_multiplier_0' is too narrow. (DDX-2)

can anyone help me please to resolve this problem,

thank you in advance,

Aminos
 

Are the ports different sizes? Post the HDL that you're tyring to synthesize.
 

the ports are diffrent sizes but i m using just the bits that i need:
example
suppose that a : std_logic_vectot (5 downto 0)
an b : std_logic_vector (10 downto 0),
i put in my vhdl code:
a => b(5 downto 0),

the functional simulation (Modelsim) before the synthezis works correctly, the pbl is during the synthezis
 

a => b(5 downto 0)

should be:

a <= b( 5 downto 0);
 

yes i know that but this signal is an instanciation of component:
half_multiplier:multiplier
port map(
a => b (5 downto 0),
.
.
.
);
 

I don't know if all synthesizers can handle subelement associations. Can you try another synthesizer?
 

unfortunatly no, cause we re supposed to work just on this ynthesizers, do you have any other idea to avoid this problem?
 

Other than make the bus widths the same, no.
Download a free synthesizer like Xilinx ISE and test it out. Maybe it's just DC that's the problem. Weird.
 

    Aminos

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