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Subthreshold MOS mismatch: How bad does it really get?

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gszczesz

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I need to obtain some quasi-quantitative estimate of mismatch of a PMOS/NMOS with very low current densities, suspected to be in subthreshold.

I know sub-threshold operation degrades mismatch, but I've never seen quantitative measures. Anyone know how bad it gets, or how to estimate it (rule-of-thumbs are o.k.)?

As a bonus, does anyone know how sub-threshold is sensitive to time + temperature?

Greg
 

As expressed in mV of Vth, the sub-threshold mismatch is 2-3 times bigger than the strong inversion one for the same size transistors. This is my experience.
 

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    gszczesz

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Thank you for the rule-of-thumb.

Does anyone have an equation or something more predictive?

Greg
 

Be careful saying that mismatch in WI worsens. That is for a given transistor size. Nevertheless, in most cases the design is based on a given current basis. Si to get your transistors into WI, the size must increase and this normally improves matching.
 

Hi,
As Steer has mentioned, the current mismatch can be dramatic for a few mV.
If you observe the Id equation:
=Ido exp[(Vgs-Vth-Voff)/nVt]
Ido=2nβ(Vt)²

try varying the vth by 5 to 20mv and ibserve the change in I

Agreed that as W and L increase matching does increase, but due to high temperature in fabrication process, Vth mismatch can take place and do take place. If by chance you have a metal laid over gate of one of these transistors you wouid surely observe Vth variation between transistors and large sizes would be of no help.
If you need to bias circuit at large distance from the current mirror, and you are doing voltage biasing, you are bound to observe Vth mismatch in transistors immaterial of the size.
 

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