how to remove timing conflicts

Hi everyone,

I am troubled with the problem of timing conflicts in my post place and route simulation. For almost a beginner in FPGA designing, I am absolutely outwtitted at this. My behavioral simulation works perfectly fine but the post layout simulation cracks out on me. Could anyone guide me how should I go about removing the problem? I understand what causes timing conflicts in digital circuits but how can I remove them in the environment of an FPGA i dont know. So please tell me:

1) Where should I look into for reliable details about max clock freq, max setup and hold time and etc or the circuit.
2) There is something about 'slack' in leonardo spectrum's synthesis report. What is it and its significance
3) Finally how these conflicts are removed? Does it require changing my code, defining constraints or both and how can my simulator be of any help here besides showing me just the waveform.

The tools that I use are : Xilinx ISE 6.1i SP 3, ModelSim SE 5.7G and Leonardo Spectrum 2005_a82 for synthesis.

Thanks in advance

i believe the slack can either be removed by changing the frequency of operation..or if you could view the critical path,you might wanna change the logic in that path,so as reduce the slack.