why after synthesis have assign?

synthesis assign

After i synthesis a chip, and generate a netlist. I read the netlist find at netlist have "assign" command . Don't the "assign" effect backend tools such as astro?

dc synthesis remove assigns

If you don't fix assign, the astro may fail to pass drc.
There are many articles to explain in solvnet, though they may not take effect as you expect in fact.
You can write a script to modify the netlist.

set_fix_multiple_port_nets

Sometimes synopsys gives "assign" statement in its output codes, for example,
when it need to convert one data type from wire to reg.

Those assign statement can cause problem in both VerilogIn and Silicon Ensemble. NSC has codes to remove those lines, however, it results in connections broken, and you'll have to fix that somehow.

To tell synopsys NOT using assign statement, do the following in dc_shell (command window in design_analyzer):
1. verilogout_no_tri=true
2. set_fix_multiple_port_nets -all -buffer_constants

use man to see manuals of those variables.

assign synthesis

use this
"set_fix_multiple_port_nets -all -buffer_constants -feedthroughs"
before compile , your problem will solved.

assign in netlist

use this command, it will prevent adding assign in your netlist.

set verilogout_equation false

synopsys assign

I found sometimes, it also works:
change_name -rule verilog

You can try...
This just fix those assigns except feedthrough...

remove assign dc_shell

Sometimes if your codes have some error, the DC compile the codes failed. This will generate assign in your netlist even you have use "set_fix_multiple_port_nets -all -buffer_constants".
So don't forget to check your RTL codes.

set_dont_touch_network assign

Hello!


Why is it happen (these assigns) if I have used the commands above in version 2003.03 (here the assigns dissappear) and with the same settings in 200.06 I still get "assigns". Could be because of the DC version?

Thanks in advance!

assign statements in netlist

hi,
yes, after you used all above command, you will still find assign in your netlist. the only way you can do in synthesis is to compile -inc for several times. maybe you can get a good netlist. And maybe you can try rtlcompiler from c@dence.
And if you dont want to do that ugly job , you can use p&r tools socencounter and setAssignbuf 1, and you can work around it.
Best Regards.

synopsys how to get assign in the netlist

linuxluo said:

hi,
yes, after you used all above command, you will still find assign in your netlist. the only way you can do in synthesis is to compile -inc for several times. maybe you can get a good netlist. And maybe you can try rtlcompiler from c@dence.
And if you dont want to do that ugly job , you can use p&r tools socencounter and setAssignbuf 1, and you can work around it.
Best Regards.

Click to expand...

I don't think that doing compile -incr is a good solution... It may worsen the result.. anyway.. interesting thing....

10x ;-)

fix multiple ports nets

maybe you can check if you "set_dont_touch_network" on that net.

assign statement in netlist

after using set_fix_multiple_ports, assigns might be there. because that assigns logic is in the submodules. using scripts only we need to remove the assigns.

avoid verilog assign after synthesis

If you use dc to synthesis, you can use :
verilogout_no_tri=true
set_fix_multiple_port_nets -all -buffer_constants
not only before compile, but also use them before write netlist .

assign con synopsys

Can this assign be avoided by good coding style?

remove assign dc

check your design, If theree are the floating post in your module, The assign staements will are written in to the netlist

verilogout_equation

Hi,

Don't get over react in removing assign. All the backend tool I know can accept this.

First, I can think of two reasons why assign is present:

1. A net is driving two output ports. While Verilog support this, alot of other tools (e.g. schematic capture) do not support it (due to the net connect to the output port should be named the name of the port, so we end up with a net with 2 different names, which is bad).

2. A input port connect directly to an output port.

For 1, the tool should insert a buffer to remove the assign. For 2, which it is possible to also insert a buffer to remove the assign, it is not productive. Depend on the coding style (and sometime due to parameterized design), alot of buffer may be needed.


Some details on (2). There is almost no way to code in verilog that has a connection between an input port to an output port without using assign statement. The closest I know is:

module abc (A, A);
inout A;
endmodule.

Verilog supports connection in the port list (Cadence netlist using this for bus ripper). However, the above example is bi-directional, but assign is uni-directional. Don't try to use the above syntax; alot of tool will go burst.

Regards,
Eng Han
www.eda-utilities.com

synplify assigns in netlist

Hi leeenghan & all,
Thanks for the brief notes on why synthsis tool inserts assigns statements
and various views
i was not able to understand how iur going to avoid a net with 2 different names, which is bad by adding buffer
thanks

synopsys　assign

DC 2004.12 has bug, can not remove the assign in the generated netlist, 0406 can do