Design for testability (DFT) and fault simulation (FS)

hi,
could you explain fault simulation?
thx

Re: dft question

design for testability = DFT.

and fault simulation = FS.

regardign FS: it's simulation of circuit with injection of fault within it. so you need three component
1. circuit defination / model / hdl /configuration (intended circuit, fault free)
2. fault model ::= which introduce fault in the circuit while simulation is run
3. golden output ::= desired output of the circuit for given input combination

example. take a CMOS inverter of with p and n transister
with one input one output

1. so circuit netlist is your circuit defination
2. consider stuck-at 1 or stuck-at 0 fault for each transister's input and output
3. for given combination of input (here only one bit as input so
input = 0 golden output =1.
input = 1 golden output =0.

and then simulated circuit 1 with fault model 2 (instead of normal transister model) and compare the output of circuit with expected golden output 3.

if actual output deviates from golden that mean fault can be detectable with given input combination.

if given fault is not detectable with any of input combination then you need to modify you design such that: desired functionality of circuit doesnot change but intended fault can be identified. such techniques ate called "Design For Testability" DFT.

Further reading :
\1\ Fault simulation to find minimal test vector.
\2\ DFT technique to assist *test* of design in later phase.

regards...ue

Re: dft question

thx for reply. is it done before or after ATPG?

dft question

Fault simulation is a process that help us to find the best test vector set.
You should carry out this proccess in parallel with ATPG. It means that:
The first you should generate a test vector set. And then, you perform fault simulation to optimize this vector set to reduce test time, test cost,...

Hope that will help you! If it helps you, pls don't forget give me a HELP to get some points.

Re: dft question

Hi

Fault simulation actually mimics the production test. The fault simulator deliberately injects faults into the circuit and then runs the test program and compares the output with the golden one and if there is deviation then it decides that the intended fault is detected. It then uses this information to find fault coverage.