ADC Testing in Cadence : Verilog A

adc testing

Hi frns,
In Cadence (Spectre, 445), there is some inbuilt library for ideal DAC/DAC etc. These are based on Verilog A. The library names are "ahdlLib" or "analogLib".

Now, While testing an designed ADC, at schematic level, one way is to calculate by hand the digital output bits and compare it with the analog value. This is OK with stair case ip or even ramp. But for sinusoid of high frequency (little less than nyquist), it is hard to consider the transient efefct and delays.

One solution is to convert the ADC output bac to Analog by an ideal DAC and go for fft. This is also available, as told earlier.

Problem: While simulating the ideal DAC, it is giving flat output (0V). I have checked the parameters etc.

Also, if you have any other idea to resolve the problem, will be appreciated.

Thans in advance,
Sankudey

adc veriloga

Hi all,
The problem stated above has been solved in the following way....

an IDEAL DAC was designed by using the "vcvs" (Voltage Controlled Voltage Source) available in analogLib of cadence. This vcvs takes one voltage (two port) and gives out another voltage (two port). It has its "gain" as its parameter.

The equation of the D/A converter was mapped by this mathematically....simple A=b0 + b1.2(^1) + b2.2(^2)....from these the gain can be calculated easily....
when it is connected to the DAC output....it is giving back the analog signal fed to the DAC...only a little time dealy will appear....

by the way....the original problem remains the same....HOW TO RUN Verilog A from cadence....a tutorial could also be of help....

with regards...
sankudey

verilog cadence

hi sankudey,
Actually you can do fft in spectre or dump the data of adc out to matlab to do fft and the ideal dac can be modeled in matlab,of course u can use an ideal dac in cadence then only one output signal is to be dumped out.

as to veriloga, u can create an veriloga view of the cell using verilog-a editor. u can refers to the cadence help file of veriaref.pdf in $CDS_INST_DIR

verilog a cadence

Hi,
I have searched the path u mentioned but couldn't find the file u mentioned. That may be due to old version of the cadence we installed. Any way ur information has helped me.

I will be more thankful to u if u could send me the the veriaref.pdf file (thru eda board or mail or any thing.

Thanks,
sankudey

dac veriloga

The path maybe :
$CDS_INST_DIR/doc/veriaref


Good Luck

fft veriloga

Hi HanGu,
I have checked that path. Actually the I have searched by "find" sitting in the mother directory. But, I don't find it. It would really be helpful if you give me the document, if u have it.

looking for ur help...
sankudey

adc test cadence tutorial

sankudey said:

Hi HanGu,
I have checked that path. Actually the I have searched by "find" sitting in the mother directory. But, I don't find it. It would really be helpful if you give me the document, if u have it.

looking for ur help...
sankudey

Click to expand...

I would be also interested in getting the file. BTW, I really need to find out how to do an fft in Cadence and up to now I have no ideea. CAn anybody help me?
Thanks

cadence verilog

sankudey said:

Hi,
I have searched the path u mentioned but couldn't find the file u mentioned. That may be due to old version of the cadence we installed. Any way ur information has helped me.

I will be more thankful to u if u could send me the the veriaref.pdf file (thru eda board or mail or any thing.

Thanks,
sankudey

Click to expand...

Hi Sankudey,
Here is the verilog-A reference file (veriaref.pdf) that you requested.

Bharath

veriloga adc

Hi cretu,
To do the fft...follow the steps below...
1. preapared with a 'wave' in the wave viewer and the calculator
2. press the button 'wave' in the calculator..
3. now select the wave u wnat to do fft....the name of the wave will come to the calculator
4. now press 'special function' in the calculator....
5. from the drop-down list select 'dft'
6. now give ur required things....generally we select 'rectengular'...
7. if u need the plot in db (10 / 20)...press it in the calculator....
8. now press 'plot' or 'erplot' in the calculator...
--> u will get the output...

hope would help...
sankudey

verilog a voltage ramp

which one is more accurate..using an ideal DAC or dft?

verilog a ramp

Hi uckingcu,
Actualyy both of them are different methods of measuring the ENOB. By ideal DAC and associated setups you can measure the error in time domain and from that you can calculate ENOB. By DFT you can straight way calculate ENOB in frequency domain.
Ideally, both of them should be performed on the same device with a FULL SCALE sinusoid excitation and the results from both of them should be compared. They should closely match if everything is right.

sankudey

cadence source file config view post

by the way....the original problem remains the same....HOW TO RUN Verilog A from cadence....a tutorial could also be of help....

Click to expand...

The easiest way: Just make a symbol view for your cell (verilog-a) and include the symbol view into a schematic(testbench), if you have more views you can make a config view.