samcheetah
Advanced Member level 2
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log of exponentials
i have heard that a divide by 2 circuit takes alot of space in FPGA so it is usually implemented with a shifter.
now the problem is that i have to calculate both logs and exponentials and i think it wont be much efficient in terms of silicon area. does any one know how to do this?
i have heard that a divide by 2 circuit takes alot of space in FPGA so it is usually implemented with a shifter.
now the problem is that i have to calculate both logs and exponentials and i think it wont be much efficient in terms of silicon area. does any one know how to do this?