Time Borrowing in latches

time borrowing

Hi,

Can anyone clearyly tell me what is Time borrowing concept in latches? If possible give a good link

time borrowing in latches

Time borrowing means one latch takes the (a portion of ) clock period from its adjuscent latches by inserting buffers in clock network in proper position.

latch time borrowing

anjali said:

Time borrowing means one latch takes the (a portion of ) clock period from its adjuscent latches by inserting buffers in clock network in proper position.

Click to expand...

yes. if you are interesting in this you can read this book more detail.
something about this :
---------------------------------------------
Slack passing is possible with level-sensitive latches or cycle stealing, by
careful scheduling of the arrival of the clock edges at different registers.
Multi-phase clocking will not be a viable solution in the deep submicron,
because of signal integrity issues and the increasing difficulty of distributing
several clocks across the chip [36].
If the latch inputs arrive within the window while the latches are
transparent, the setup time and clock skew have far less impact on the clock
period. Some high speed pulsed flip-flops have about zero setup time [30],
but they are not transparent, so the impact of the clock skew is not reduced.
As ASICs have large clock skew, latches have substantial benefits for
reducing the clock period.
Also, level-sensitive latches reduce the impact of inaccuracy of wire load
models and process variation. The clock period is not limited by the delay of
the slowest pipeline stage, because of slack passing. Adjusting the clock
skew after layout and extraction of parasitic capacitances can compensate for
wire load model inaccuracies. However, changing the clock trees requires
additional layout iterations.


Clock-related timing issues are tutorially reviewd in Chapter 3
(Chinnery). Chapter 7 (Tensilica – latches) describes a prototype tool that
automatically converts a gate net list with flip-flops to use latches –
experimental results of 10% to 20% speed improvement are reported for a
commercial synthesizable ASIC in a high-performance standard cell ASIC
flow.
----------------------------------
this attach is about the timing theory of latch-base design. and it is good for reading

time borrowing latch

As mentioned in Section 7.1, unlike an edge-triggered FF, a level-clocked latch
is transparent during the active period of the clock. This makes the analysis
and design of level-clocked circuits more complex than edge-triggered circuits,
since combinational blocks are not insulated from each other by the memory
elements, and multicycle paths are possible when the data is latched during the
transparent phase of the clock. Even though this transparent nature introduces
an additional level of complexity to the design phase, level-clocked circuits are
often used for high-performance designs since they offer more flexibility than
edge-triggered circuits, both in terms of the minimum clock period achievable
and the minimum number of memory elements required.
As an illustration of this notion, consider the simple circuit in Figure 7.4
with unit delay gates and a single-phase clocking scheme with a 50% duty
cycle. Let us assume that the data signals are available at the primary inputs
at the falling edge of the clock, and must arrive at the primary outputs before
the appropriate falling edge, several clock cycles later. At the level-triggered
latch L1, the data may depart at any time while the clock is high. A data
signal in this circuit is allowed precisely two clock periods to reach the primary
output from the primary input.
We will now use this example to demonstrate the advantage of using level
clocked circuits over edge-triggered circuits. For simplicity, we will assume zero
setup and hold times here. Consider the operation of the circuit under a clock
period of 2 units; notice that the path delay between latch L1 and the output
is more than the clock period. However, the circuit works correctly due to the
transparent nature of the latches. As shown in the figure, the data departs from
the IN node at time 0, arrives at and departs from the latch L1 at time 1, and
is latched at the output at time 4, which corresponds to the onset of the second
clock edge. In contrast, if L1 were an edge-triggered FF, then a clock period of
2 units would have been untenable, since the clock period would correspond to
the largest combinational block delay, which implies that the minimum possible
clock period would have been 3 units. This practice of using the active period of
138 TIMING
the clock in a level-clocked circuit to allow combinational paths to have a delay
of more than the clock period is referred to variously as either cycle borrowing,
cycle stealing, slack stealing, or time borrowing.
For edge-triggered circuits, the insulating nature of the memory elements
leads to the requirement that the delays through all combinational logic paths
must be less than the clock period, with an allowance for setup and hold time
constraints. Therefore, timing constraints need only be enforced between FF’s
connected by a purely combinational path. For level-clocked circuits, due to
cycle borrowing, the delay through a combinational logic path may be longer
than one clock cycle, as long as it is compensated by shorter path delays in
subsequent cycles.
To ensure that the extra delay is compensated, we must enforce timing
constraints between a latch and every other latch reachable from it via a path
that traverses combinational logic, and possibly multiple latches.
Example. Consider a linear N stage acyclic pipeline with N + 1 memory
elements If these memory elements were edge-triggered FF’s,
then we would need only N timing constraints (from the path
). However, if these memory elements were to be level sensitive latches,
then we would need N · (N +1)/2 timing constraints and
to check the correctness of multicycle paths. In the presence of feedback
paths, the timing analysis of level-clocked circuits would become even more
complex.
As will soon be shown, some of this complexity can be reduced by the introduction
of an appropriate set of intermediate variables.

latch borrowing

to meet the timing in the design.
tool put a latch to adjust timing mismatch.
read SOLD and SNUG article to get more pic oriented approach

time borrowing flip flop

To get more idea
go to the rabey timing issues chapter in that he explained about it with an example


Hi Aravind
where can i get the SOLD n SNUG aritcle?

latch time borrow

pra, u have 2 register with synopsys.com 1st, only then u can access these materials.

latch timing borrow

hi, nmtr,

The material you provided belongs to which book?
thanks!

latch borrow time

thanks for the material

time borrowing in latch

hiiii any one could u please send me DFT in ASIC material or plz suggest me any ref. books

The book referenced is Closing the Gap Between ASIC & Custom by David Chinnery and Kurt Kuetzer