How to translate Verilog (GATE Level) to Spice(with Standard Cell)?

Does any one know how to translate Verilog (GATE Level) to Spice(with Standard Cell)?
Thanks.

verilog2spice

Is this kind of process possible?
you may need synthisiser or such befor this stage.

spice to verilog

You can use cadence tools to read in a verilog netlist then generate a spice netlist.

edif to spice

To Jaz:
I only have SPICE CELL, I don't have Standard Cell Library for Cadence. I have ever used Verilog In of Cadence to generate netlist. The Cadence will create symbol for Standard cell.But the pin order of the symbol doesn't match to Spice Cell. Would you tell me how to chang the pin order to match the SPICE CELL?
Thnaks a lot.

v2s verilog to spice

May u can try the ECS (Cohesion ).
They have ASCII library format.
And there are SDK which can build ur own script to solve ur problem by programing their tool.
I saw there is a sample script to translate
verilog into symbol lib.

spice 2 verilog

If you only have to translate a Verilog Gate Level netlist into spice you should do that with a script. The gate level netlist is flat and uses unordered pins. That is in contrast to spice where the order is In/Bidirectional/Out and then lexical. So the script have to order the pins. Cadence for example does store internal regarding some order. That is why sometime if you edit Symbol and Schematic the order get confused.

site:www.edaboard.com spef syntax

ECO change netlist
1. verilog --> design analyzer --> edif output ---> ECS6.0 edit & change
cell--> spice

2. verilog --> gatevision ---> edif output ---> ECS6.0 edit & change cell-->
spice

3. RC-extract debug
SPEF netlist --> spicevision Pro

4. use Layout tool Hercula_nettran function

5. nassda tool
v2s to convert verilog netlist to spice
Command syntax
v2s <verilogFile> -s <cellSpiceFile> -o design.sp
<verilogFile>: input verilog file
<cellSpiceFile>: ASIC cells spice netlist
In case a memory block exists in the design, the simulation time can become
very long. As a result, it is recommended to use an equivalent skeleton (an
empty shell with only capacitors connected to the input ports) to replace
the memory block in the design.
A utility lib2spice can generate the skeletons from the .lib files.
lib2spice –i <libFile> -o <spiceFile>
<libFile>: input Synopsys .lib file
<spiceFile>: output skeleton file

6. verilog ---> DA --> edif --> viewdraw --> spice

cadence verilog to hspice

i want , too

gate level netlist sample verilog

you must have spice netlist of all cells, then use some netlist translator to translate the verilog netlist into spice netlist.
The translated netlist only shows the connection of std cells, same as edif/sch or hdl netlist, but you can include the spice netlist of std cells as subckt, then you can do simulation of your circuits.

how to convert verilog to gate level

As i know , na$$da h$im contain a translator of verilog2spice !

liberty file from spice scripts

I do not think verilog has enough info to change into spice. You can change from spice to verilog.

translateur netlist verilog to spice

hsim have utility called "v2s"

it can convert gate level verilog , and mapping to standard_cell
library , then convert verilog netlist to spice netlist ..

you can get V2S ( PC version is "dos" command ..)

generating a spice file from verilog file

Nobody said:

May u can try the ECS (Cohesion ).
They have ASCII library format.
And there are SDK which can build ur own script to solve ur problem by programing their tool.
I saw there is a sample script to translate
verilog into symbol lib.

Click to expand...

ESC NOW in Xilinx ISE ?